And here is theoutput with diag-switch?= true, diag-level = max:
Software Power ON
@(#) Ultra Enterprise 3.2 Version 30 created 2002/10/25 14:03
CPU = 0000.0000.0000.000a
Probing keyboard Done
5,0>
5,0>@(#) POST 3.9.30 2002/10/25 14:04
5,1>
5,0>Copyright 2002 Sun Microsystems, Inc. All rights reserved.
5,1>@(#) POST 3.9.30 2002/10/25 14:04
5,0>
SelfTest Initializing (Diag Level 10, ENV 00004001) IMPL 0011 MASK 20
5,1>Copyright 2002 Sun Microsystems, Inc. All rights reserved.
5,0>Board 5 CPU FPROM Test
5,1>
SelfTest Initializing (Diag Level 10, ENV 00000000) IMPL 0011 MASK 20
5,0>Board 5 Basic CPU Test
5,0> Set CPU UPA Config and Init SDB Data
5,0> SRAM Mode = 22, Clock Mode = 4:1, PCON = 6b3, MCAP = 0
5,0>Board 5 MMU Enable Test
5,0> DMMU Init
5,0> IMMU Init
5,0> Mapping Selftest Enabling MMUs
5,0>Board 5 Ecache Test
5,0> Ecache Probe
5,0> Ecache Tags
5,1>Board 5 CPU FPROM Test
5,1>Board 5 Basic CPU Test
5,1> Set CPU UPA Config and Init SDB Data
5,1> SRAM Mode = 22, Clock Mode = 4:1, PCON = 6b3, MCAP = 0
5,1>Board 5 MMU Enable Test
5,1> DMMU Init
5,1> IMMU Init
5,1> Mapping Selftest Enabling MMUs
5,1>Board 5 Ecache Test
5,1> Ecache Probe
5,1> Ecache Tags
5,0> Ecache Quick Verify
5,1> Ecache Quick Verify
5,0> Ecache Init
5,1> Ecache Init
5,0> Ecache RAM
5,1> Ecache RAM
5,0> Ecache Address Line
5,0> Configure Ecache Limit
5,0>Ecache Size = 00400000, Limited to 00400000
5,0>Board 5 FPU Functional Test
5,0> FPU Enable
5,0>Board 5 Board Master Select Test
5,0> Selecting a Board Master
5,0>Board 5 FireHose Devices Test
5,1> Ecache Address Line
5,1> Configure Ecache Limit
5,1>Ecache Size = 00400000, Limited to 00400000
5,1>Board 5 FPU Functional Test
5,1> FPU Enable
5,1>Board 5 Board Master Select Test
5,1> Selecting a Board Master
5,0>Board 5 Address Controller Test
5,0> AC Initialization
5,0> AC DTAG Init
5,0>Board 5 Dual Tags Test
5,0> AC DTAG Init
5,0>Board 5 FireHose Controller Test
5,0> FHC Initialization
5,0>Board 5 JTAG Test
5,0> Verify System Board Scan Ring
5,0>Board 5 Centerplane Test
5,0> Centerplane Join
5,0>Setting JTAG Master
5,0>Clear JTAG Master
5,0>Board 5 Setup Cache Size Test
5,0> Setting Up Cache Size
5,0>Board 5 System Master Select Test
5,0> Setting System Master
5,0>POST Master Selected (JTAG,CENTRAL)
5,0>Board 16 Clock Board Test
5,0> Clock Board Initialization
5,0> Clock Board Temperature Check
5,0>Board 16 Clock Board Serial Ports Test
5,0>Board 16 NVRAM Devices Test
5,0> M48T59 (TOD) Init
5,0>Board 5 System Board Probe Test
5,0> Probing all CPU/Memory BDA
5,0> Probing System Boards
5,0> Probing CPU Module JTAG Rings
5,0>Setting System Clock Frequency
5,0> CPU Module mid 10 Checked in OK (speed code = 7)
5,0> CPU mid 11 Version=00170011.20000507
5,0> CPU Module mid 11 Checked in OK (speed code = 7)
5,0> CPU mid 18 Version=00170011.20000507
5,0> CPU Module mid 18 Checked in OK (speed code = 7)
5,0> CPU mid 19 Version=00170011.20000507
5,0> CPU Module mid 19 Checked in OK (speed code = 7)
5,0>System Frequency (MHz),fcpu=336, fmod=168, fsys=84, fgen=336
5,0>TESTING BOARD 1
5,0>Board 1 JTAG Test
5,0> Verify System Board Scan Ring
5,0>Board 1 Centerplane Test
5,0> Centerplane Check
5,0>Board 1 Address Controller Test
5,0> AC Initialization
5,0>Setting Freq to 25MHZ
5,0> AC DTAG Init
5,0>Board 1 FireHose Controller Test
5,0> FHC Initialization
5,0>Board 1 NVRAM Devices Test
5,0> M48T59 (TOD) Init
5,0>TESTING BOARD 3
5,0>Board 3 JTAG Test
5,0> Verify System Board Scan Ring
5,0>Board 3 Centerplane Test
5,0> Centerplane Check
5,0>Board 3 Address Controller Test
5,0> AC Initialization
5,0>Setting Freq to 33MHZ
5,0> AC DTAG Init
5,0>Board 3 FireHose Controller Test
5,0> FHC Initialization
5,0>Board 3 NVRAM Devices Test
5,0> M48T59 (TOD) Init
5,0>TESTING BOARD 7
5,0>Board 7 JTAG Test
5,0> Verify System Board Scan Ring
5,0>Board 7 Centerplane Test
5,0> Centerplane Check
5,0>Board 7 Address Controller Test
5,0> AC Initialization
5,0>Setting Freq to 33MHZ
5,0> AC DTAG Init
5,0>Board 7 FireHose Controller Test
5,0> FHC Initialization
5,0>Board 7 NVRAM Devices Test
5,0> M48T59 (TOD) Init
5,0>Re-mapping to Local Device Space
5,0>Begin Central Space Serial Port access
5,0>Enable AC Control Parity
5,0>Hotplug Trigger Test
5,0>Init Counters for Hotplug
5,0>Board 5 Cross Calls Test
5,0>Board 5 Environmental Probe Test
5,0> Environmental Probe
5,0>Checking Power Supply Configuration
5,0>Power is adequate, load 5 ps 3
5,0>Use existing memory configuraton
5,0>TESTING IO BOARD 1
5,0>Board 1 I/O FPROM Test
5,0>@(#) iPOST 3.4.30 2002/10/25 14:03
5,0> TESTING IO BOARD 1 ASICs
5,0> TESTING SysIO Port 0
5,0>Board 1 SysIO Registers Test
5,0> SysIO Register Initialization
5,0> SysIO RAM Initialization
5,0>Board 1 SysIO Functional Test
5,0> Clear Interrupt Map and State Registers
5,0>Board 1 OnBoard IO Chipset (SOC) Test
5,0> TESTING SysIO Port 1
5,0>Board 1 SysIO Registers Test
5,0> SysIO Register Initialization
5,0> SysIO RAM Initialization
5,0>Board 1 SysIO Functional Test
5,0> Clear Interrupt Map and State Registers
5,0>Board 1 OnBoard IO Chipset (FEPS) Test
5,0>IO BOARD 1 TESTED
5,0>TESTING IO BOARD 3
5,0>Board 3 I/O FPROM Test
5,0>@(#) iPOST 3.0.30 2002/10/25 14:03
5,0> TESTING IO BOARD 3 ASICs
5,0> TESTING Psycho Port 0
5,0>Board 3 Psycho Basic Test
5,0>Board 3 Psycho Functional Test
5,0> Init Psycho
5,0>Board 3 Psycho Error Test
5,0> Init Psycho
5,0>Board 3 OnBoard IO Chipset (Cheerio) Test
5,0> Init Cheerio
5,0> TESTING PSYCHO Port 1
5,0>Board 3 Psycho Basic Test
5,0>Board 3 Psycho Functional Test
5,0> Init Psycho
5,0>Board 3 Psycho Error Test
5,0> Init Psycho
5,0>Board 3 OnBoard IO Chipset (ISP1040) Test
5,0> ISP PCI Configuration Space Validation
5,0>IO BOARD 3 TESTED
5,0>TESTING IO BOARD 7
5,0>Board 7 I/O FPROM Test
5,0>@(#) iPOST 3.0.30 2002/10/25 14:03
5,0> TESTING IO BOARD 7 ASICs
5,0> TESTING Psycho Port 0
5,0>Board 7 Psycho Basic Test
5,0>Board 7 Psycho Functional Test
5,0> Init Psycho
5,0>Board 7 Psycho Error Test
5,0> Init Psycho
5,0>Board 7 OnBoard IO Chipset (Cheerio) Test
5,0> Init Cheerio
5,0> TESTING PSYCHO Port 1
5,0>Board 7 Psycho Basic Test
5,0>Board 7 Psycho Functional Test
5,0> Init Psycho
5,0>Board 7 Psycho Error Test
5,0> Init Psycho
5,0>Board 7 OnBoard IO Chipset (ISP1040) Test
5,0> ISP PCI Configuration Space Validation
5,0>IO BOARD 7 TESTED
5,0>Probing for Disk System boards
5,0>Board 5 System Interrupts Test
5,0>
5,0> System Board Status
5,0>-----------------------------------------------------------------
5,0> Slot Board Status Board Type Failures
5,0>-----------------------------------------------------------------
5,0> 0 | Not installed | |
5,0> 1 | Normal | IO Type 1 |
5,0> 2 | Not installed | |
5,0> 3 | Normal |+IO Type 3 |
5,0> 4 | Not installed | |
5,0> 5 | Normal |+CPU/Memory |
5,0> 6 | Not installed | |
5,0> 7 | Normal |+IO Type 3 |
5,0> 8 | Not installed | |
5,0> 9 | Normal |+CPU/Memory |
5,0> 16 | Normal | Clock Board |
5,0>-----------------------------------------------------------------
5,0>
5,0> CPU Module Status
5,0>-----------------------------------------------------------------
5,0> MID OK Cache Speed Version
5,0>-----------------------------------------------------------------
5,0> 10 | y | 4096 | 336 | 00170011.20000507
5,0> 11 | y | 4096 | 336 | 00170011.20000507
5,0> 18 | y | 4096 | 336 | 00170011.20000507
5,0> 19 | y | 4096 | 336 | 00170011.20000507
5,0>-----------------------------------------------------------------
5,0>System Frequency (MHz),fcpu=336, fmod=168, fsys=84, fgen=336
5,0> Populated Memory Bank Status
5,0> bd # Size Address Way Status
5,0> 5 2048 0 4 Normal
5,0> 5 2048 2 4 Normal
5,0> 9 2048 1 4 Normal
5,0> 9 2048 3 4 Normal
5,0>
5,0>
POST COMPLETE
5,0>Entering OBP
Switching to high addresses
Setting up TLBs Done
MMU ON
PC = 0000.01ff.f000.1cb8
PC = 0000.0000.0000.1d24
Decompressing into Memory Done
Size = 0000.0000.0006.d8c0
ttya initialized
Using POST's System Configuration
Setting up memory
Starting CPU ID 11
Starting CPU ID 18
Starting CPU ID 19
fhc ac simm-status environment sram flashprom SUNW,UltraSPARC-II SUNW,UltraSPARC-II
fhc ac simm-status environment sram flashprom SUNW,UltraSPARC-II SUNW,UltraSPARC-II
Probing UPA Slot at 2,0 sbus fhc ac environment flashprom eeprom sbus-speed counter-timer
Probing UPA Slot at 3,0 sbus counter-timer
Probing UPA Slot at 6,0 pci pci fhc ac environment flashprom eeprom sbus-speed counter-timer
Probing UPA Slot at 7,0 pci pci counter-timer
Probing UPA Slot at e,0 pci pci fhc ac environment flashprom eeprom sbus-speed counter-timer
Probing UPA Slot at f,0 pci pci counter-timer
Probing /sbus@2,0 at d,0 SUNW,soc
Probing /sbus@2,0 at 1,0 cgsix
Probing /sbus@2,0 at 2,0 Nothing there
Probing /sbus@3,0 at 3,0 SUNW,hme SUNW,fas sd st
Probing /sbus@3,0 at 0,0 SUNW,socal sf ssd sf ssd
Probing /pci@6,4000 at 1 pci108e,1000 SUNW,hme
Probing /pci@7,4000 at 3 SUNW,isptwo sd st
Probing /pci@6,2000 at 2 Nothing there
Probing /pci@7,2000 at 2 Nothing there
Probing /pci@e,4000 at 1 pci108e,1000 SUNW,hme
Probing /pci@f,4000 at 3 SUNW,isptwo sd st
Probing /pci@e,2000 at 2 Nothing there
Probing /pci@f,2000 at 2 Nothing there
Using POST's System Configuration
Setting up memory
Starting CPU ID 11
Starting CPU ID 18
Starting CPU ID 19
fhc ac simm-status environment sram flashprom SUNW,UltraSPARC-II SUNW,UltraSPARC-II
fhc ac simm-status environment sram flashprom SUNW,UltraSPARC-II SUNW,UltraSPARC-II
Probing UPA Slot at 2,0 sbus fhc ac environment flashprom eeprom sbus-speed counter-timer
Probing UPA Slot at 3,0 sbus counter-timer
Probing UPA Slot at 6,0 pci pci fhc ac environment flashprom eeprom sbus-speed counter-timer
Probing UPA Slot at 7,0 pci pci counter-timer
Probing UPA Slot at e,0 pci pci fhc ac environment flashprom eeprom sbus-speed counter-timer
Probing UPA Slot at f,0 pci pci counter-timer
Probing /sbus@2,0 at d,0 SUNW,soc
Probing /sbus@2,0 at 1,0 cgsix
Probing /sbus@2,0 at 2,0 Nothing there
Probing /sbus@3,0 at 3,0 SUNW,hme SUNW,fas sd st
Probing /sbus@3,0 at 0,0 SUNW,socal sf ssd sf ssd
Probing /pci@6,4000 at 1 pci108e,1000 SUNW,hme
Probing /pci@7,4000 at 3 SUNW,isptwo sd st
Probing /pci@6,2000 at 2 Nothing there
Probing /pci@7,2000 at 2 Nothing there
Probing /pci@e,4000 at 1 pci108e,1000 SUNW,hme
Probing /pci@f,4000 at 3 SUNW,isptwo sd st
Probing /pci@e,2000 at 2 Nothing there
Probing /pci@f,2000 at 2 Nothing there
5-slot Sun Enterprise E3500, No Keyboard
OpenBoot 3.2.30, 8192 MB memory installed, Serial #10563790.
Copyright 2002 Sun Microsystems, Inc. All rights reserved
Ethernet address 8:0:20:a1:30:ce, Host ID: 80a130ce.
Rebooting with command: boot cdrom -v
Boot device: /sbus@3,0/SUNW,fas@3,8800000/sd@6,0:f File and args: -v
Loading ufs-file-system package 1.4 04 Aug 1995 13:02:54.
FCode UFS Reader 1.12 00/07/17 15:48:16.
Redirected to slice: 1
Loading: /platform/SUNW,Ultra-Enterprise/ufsboot
Loading: /platform/sun4u/ufsboot
|Size: /-\|/-\|0x704c8+/-\|/-\|/-\|/-\0x1b8d2+|/-0x2e1ba Bytes
\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/module /platform/sun4u/kernel/sparcv9/unix: text at [0x1000000, 0x10704c7] data at 0x1800000
module misc/sparcv9/krtld: text at [0x10704c8, 0x10889e7] data at 0x1849a90
module /platform/sun4u/kernel/sparcv9/genunix: text at [0x10889e8, 0x11cd177] data at 0x184eec0
module /platform/SUNW,Ultra-Enterprise/kernel/misc/sparcv9/platmod: text at [0x11cd178, 0x11cd7b7] data at 0x18a0050
module /platform/sun4u/kernel/cpu/sparcv9/SUNW,Ultra