Hi Don,
To answer your "rude" question:
1) This is the "real world" format of a subcircuit's pin order in Verilog or
CDL netlist. And I want to sort them in alphabetically order to be used in different environment such as Cadence. example:
2) The + character actually is similar to new line character. I am not sure why the netlist have it that way...
3) I was able to manually using nedit text editor to do what I want.
But it took me a while since I have to merge all fields into one line then sort it then break it into many lines again...
I just want to ask Linux experts if there is a better way of doing it ....
Best regards,
Hi. I'm sorry you found the question rude. There are a few students who run into this forum hoping to get us to do their homework for them. When that happens it is bad for us and for them.
In your above example, is .SUBCKT also "special" in that it must appear first in the output no matter what else follows, or should it be sorted too? The way you are describing the <+> character, it sounds like a continuation character indicating that it is an extension of the previous line. Can your input files contain more than one Verilog or CDL pin order list that should be sorted separately?
I am trying to setup to automatically import a series of mysql database files. I am doing manually now and its a royal pain.
All the sql files are sequentially numbered in a format of 4 numbers underscore text with spaces replaced by underscores.
example:
There are 3 databases each setup... (1 Reply)
Hi,
I am using some codes that have been ported from unix to linux, and now the sorting no longer results in the desired ordering. I'm hoping to find a way to mimic the unix sort command in linux. The input file is structured the following:
$> cat file.txt... (6 Replies)
Hello all -
I am to this forum and fairly new in learning unix and finding some difficulty in preparing a small shell script. I am trying to make script to sort all the files given by user as input (either the exact full name of the file or say the files matching the criteria like all files... (3 Replies)
I am trying to sort a file . The file looks like this:
DDFF 2 /ztpfrepos/pgr/load
DDFQ 2 /ztpfrepos/pgr/load
DDFX 2 /ztpfrepos/pgr/load
DDUA 2 /ztpfrepos/pgr/load
My command:
sort -k1 /home/c153507/Bin/OPL1.txt -o /home/c153507/Bin/OPL1.txt
The results are OK except for one line where... (4 Replies)
This is the question being asked: (Sort your data file by last name first, then by the first name second - save as first_last.) I am not quite sure of the type of sort I am being asked to perform. I have read the man pages of the sort command a few times, as well as searching online for possible... (10 Replies)
Hi Experts,
I have a filelist collected from another server , now want to sort the output using date/time stamp filed.
- Filed 6, 7,8 are showing the date/time/stamp.
Here is the input:
#----------------------------------------------------------------------
-rw------- 1 root ... (3 Replies)
I want to find all jpg files and then sort them by modification date. This is where I started.
find . -type f -name "*.jpg"
I tried to pipe a sort in there but that did not seem to work. Do I need to use xargs? (10 Replies)
Discussion started by: cokedude
10 Replies
LEARN ABOUT DEBIAN
verilog::netlist::cell
Netlist::Cell(3pm) User Contributed Perl Documentation Netlist::Cell(3pm)NAME
Verilog::Netlist::Cell - Instantiated cell within a Verilog Netlist
SYNOPSIS
use Verilog::Netlist;
...
my $cell = $module->find_cell ('cellname');
print $cell->name;
DESCRIPTION
A Verilog::Netlist::Cell object is created by Verilog::Netlist for every instantiation in the current module.
ACCESSORS
See also Verilog::Netlist::Subclass for additional accessors and methods.
$self->comment
Returns any comments following the definition. keep_comments=>1 must be passed to Verilog::Netlist::new for comments to be retained.
$self->delete
Delete the cell from the module it's under.
$self->gateprim
True if the cell is a gate primitive instantiation (buf/cmos/etc), but not a UDP.
$self->module
Pointer to the module the cell is in.
$self->name
The instantiation name of the cell.
$self->netlist
Reference to the Verilog::Netlist the cell is under.
$self->pins
List of Verilog::Netlist::Pin connections for the cell.
$self->pins_sorted
List of name sorted Verilog::Netlist::Pin connections for the cell.
$self->submod
Reference to the Verilog::Netlist::Module the cell instantiates. Only valid after the design is linked.
$self->submodname
The module name the cell instantiates (under the cell).
MEMBER FUNCTIONS
See also Verilog::Netlist::Subclass for additional accessors and methods.
$self->lint
Checks the cell for errors. Normally called by Verilog::Netlist::lint.
$self->new_pin
Creates a new Verilog::Netlist::Pin connection for this cell.
$self->pins_sorted
Returns all Verilog::Netlist::Pin connections for this cell.
$self->dump
Prints debugging information for this cell.
DISTRIBUTION
Verilog-Perl is part of the <http://www.veripool.org/> free Verilog EDA software tool suite. The latest version is available from CPAN and
from http://www.veripool.org/verilog-perl <http://www.veripool.org/verilog-perl>.
Copyright 2000-2012 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either
the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0.
AUTHORS
Wilson Snyder <wsnyder@wsnyder.org>
SEE ALSO
Verilog-Perl, Verilog::Netlist::Subclass Verilog::Netlist
perl v5.14.2 2012-05-04 Netlist::Cell(3pm)