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Full Discussion: Help with sort in Linux
Top Forums Shell Programming and Scripting Help with sort in Linux Post 302972292 by Don Cragun on Tuesday 3rd of May 2016 09:39:48 PM
Old 05-03-2016
Quote:
Originally Posted by roseriver
Hi Don,
To answer your "rude" question:
1) This is the "real world" format of a subcircuit's pin order in Verilog or
CDL netlist. And I want to sort them in alphabetically order to be used in different environment such as Cadence.
example:
Code:
 
 .SUBCKT analog_top cfg_wait[2] cfgwait[1] iso_0p9
 + d_idac_div[1] d_mux_div  rx_reserved[3]
 + VDD1 GND2

2) The + character actually is similar to new line character. I am not sure why the netlist have it that way...
3) I was able to manually using nedit text editor to do what I want.
But it took me a while since I have to merge all fields into one line then sort it then break it into many lines again...
I just want to ask Linux experts if there is a better way of doing it ....
Best regards,
Hi. I'm sorry you found the question rude. There are a few students who run into this forum hoping to get us to do their homework for them. When that happens it is bad for us and for them.

In your above example, is .SUBCKT also "special" in that it must appear first in the output no matter what else follows, or should it be sorted too? The way you are describing the <+> character, it sounds like a continuation character indicating that it is an extension of the previous line. Can your input files contain more than one Verilog or CDL pin order list that should be sorted separately?
 

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Netlist::File(3pm)					User Contributed Perl Documentation					Netlist::File(3pm)

NAME
Verilog::Netlist::File - File containing Verilog code SYNOPSIS
use Verilog::Netlist; my $nl = new Verilog::Netlist; my $fileref = $nl->read_file (filename=>'filename'); DESCRIPTION
Verilog::Netlist::File allows Verilog::Netlist objects to be read and written in Verilog format. ACCESSORS
See also Verilog::Netlist::Subclass for additional accessors and methods. $self->basename The filename of the file with any path and . suffix stripped off. $self->name The filename of the file. MEMBER FUNCTIONS
See also Verilog::Netlist::Subclass for additional accessors and methods. $self->read Generally called as $netlist->read_file. Pass a hash of parameters. Reads the filename=> parameter, parsing all instantiations, ports, and signals, and creating Verilog::Netlist::Module structures. $self->dump Prints debugging information for this file. DISTRIBUTION
Verilog-Perl is part of the <http://www.veripool.org/> free Verilog EDA software tool suite. The latest version is available from CPAN and from http://www.veripool.org/verilog-perl <http://www.veripool.org/verilog-perl>. Copyright 2000-2012 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. AUTHORS
Wilson Snyder <wsnyder@wsnyder.org> SEE ALSO
Verilog-Perl, Verilog::Netlist::Subclass Verilog::Netlist perl v5.14.2 2012-05-04 Netlist::File(3pm)
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