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DOLPHIN SLED 1.3.0 (Default branch)
12-24-2008
DOLPHIN SLED is a hierarchical schematic entrysolution with graphic linking of components,hierarchical configuration of the netlist, andmulti-language netlisting (SPICE, VHDL-AMS...).Interoperability with other schematic entry tools,particularly the ECS family (including Synario,Cohesion, and Laker-AMS) is ensured forcapitalizing on legacy designs and cooperativework. Interoperability is ensured through standarddesign exchange formats and scriptability forcustomization.License: Free To Use But RestrictedChanges:|
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fnf(1) fnf(1) NAME fnf - translate from FNF format to other formats SYNOPSIS fnf [options] DESCRIPTION FNF (Free Netlist Format) is an elaborated, hierarchical, register transfer level (RTL) netlist format used to communicate design informa- tion between frontend EDA tools. The FNF tool translates an FNF netlist to Verilog, VHDL, C, and NuSMV. OPTIONS Options are processed in the order they are received. -h OR -help Prints this information then exits. -read_fnf file Read in an FNF netlist. -write_fnf file Write out an FNF netlist. -write_nusmv file Write out an NuSMV description. -write_verilog file Write out a Verilog netlist. -write_vhdl file Write out a VHDL netlist. -write_c file Write out a C model. Appends '.c' and '.h' to file name. -write_jhdl class Write out a JHDL netlist. Appends .java to class name. EXAMPLES Building an FNF netlist from Verilog using Icarus: $ iverilog -Wall -t fnf -o my_netlist.fnf my_verilog.v Use FNF to produce a Verilog and C model: $ fnf -read_fnf my_netlist.fnf -write_verilog my_netlist.v -write_c my_netlist Use FNF to produce an NuSMV model: $ fnf -read_fnf my_netlist.fnf -write_nusmv my_netlist.smv Use FNF to produce another FNF netlist: $ fnf -read_fnf my_netlist.fnf -write_fnf my_netlist2.fnf KNOWN LIMITATIONS General o No tristate support. o No memory support. o No division or modulo operators. Icarus Verilog FNF Code Generator o Assumes ports and named signals have [n:0] ordering. o "always" blocks are constrained to the Icarus Verilog synthesizable subset. o All register clocks and asynchronous resets must be senitive on the rising edge. WARNING: No errors will be issued if a design contains "negedge". o All arithmetic operations must be unsigned. WARNING: No errors will be issued if a design contains signed operations. o Multipliers can not be embbeded in concatenations. Verilog and VHDL Model Writer o Netlist is flat. NuSMV Model Writer - 2-value model. No X's or Z's. o Inputs assumed to init to 0. o Registers are initialized to 0. VERSION 0.10.6 AUTHOR Tom Hawkins SEE ALSO FNF and Confluence : http://www.confluent.org/ Icarus Verilog : http://www.icarus.com/eda/verilog/ NuSMV : http://nusmv.irst.itc.it/ COPYRIGHT Copyright (C) 2004-2005 Tom Hawkins 31 January 2010 fnf(1)