fnf(1) [debian man page]

fnf(1) fnf(1)

NAME
fnf - translate from FNF format to other formats

SYNOPSIS
fnf [options]

DESCRIPTION
FNF (Free Netlist Format) is an elaborated, hierarchical, register transfer level (RTL) netlist format used to communicate design informa-
tion between frontend EDA tools.

The FNF tool translates an FNF netlist to Verilog, VHDL, C, and NuSMV.

OPTIONS
Options are processed in the order they are received.

-h OR -help Prints this information then exits.

-read_fnf file Read in an FNF netlist.

-write_fnf file Write out an FNF netlist.

-write_nusmv file Write out an NuSMV description.

-write_verilog file Write out a Verilog netlist.

-write_vhdl file Write out a VHDL netlist.

-write_c file

Write out a C model.
Appends '.c' and '.h' to file name.

-write_jhdl class

Write out a JHDL netlist.
Appends .java to class name.

EXAMPLES
Building an FNF netlist from Verilog using Icarus:

$ iverilog -Wall -t fnf -o my_netlist.fnf my_verilog.v

Use FNF to produce a Verilog and C model:

$ fnf -read_fnf my_netlist.fnf -write_verilog my_netlist.v -write_c my_netlist

Use FNF to produce an NuSMV model:

$ fnf -read_fnf my_netlist.fnf -write_nusmv my_netlist.smv

Use FNF to produce another FNF netlist:

$ fnf -read_fnf my_netlist.fnf -write_fnf my_netlist2.fnf

KNOWN LIMITATIONS
General

o No tristate support.

o No memory support.

o No division or modulo operators.

Icarus Verilog FNF Code Generator

o Assumes ports and named signals have [n:0] ordering.

o "always" blocks are constrained to the Icarus Verilog synthesizable subset.

o All register clocks and asynchronous resets must be senitive on the rising edge. WARNING: No errors will be issued if a design
contains "negedge".

o All arithmetic operations must be unsigned. WARNING: No errors will be issued if a design contains signed operations.

o Multipliers can not be embbeded in concatenations.

Verilog and VHDL Model Writer

o Netlist is flat.

NuSMV Model Writer

- 2-value model.
No X's or Z's.

o Inputs assumed to init to 0.

o Registers are initialized to 0.

VERSION
0.10.6

AUTHOR
Tom Hawkins

SEE ALSO
FNF and Confluence : http://www.confluent.org/

Icarus Verilog
: http://www.icarus.com/eda/verilog/

NuSMV : http://nusmv.irst.itc.it/

31 January 2010 fnf(1)

Check Out this Related Man Page

Netlist::Subclass(3pm)					User Contributed Perl Documentation				    Netlist::Subclass(3pm)

NAME

       Verilog::Netlist::Subclass - Common routines for all classes

SYNOPSIS

	 package Verilog::Netlist::Something;
	 use Verilog::Netlist::Subclass;
	 use base qw(Verilog::Netlist::Subclass);

	 ...

	 $self->info("We're here
");
	 $self->warn("Things look bad
");
	 $self->error("Things are even worse
");
	 $self->exit_if_error();

DESCRIPTION

       The Verilog::Netlist::Subclass is used as a base class for all Verilog::Netlist::* structures.  It is mainly used so that $self->warn() and
       $self->error() will produce consistent results.

MEMBER FUNCTIONS

       $self->error (Text...)
	   Print an error in a standard format.

       $self->errors()
	   Return number of errors detected.

       $self->exit_if_error()
	   Exits the program if any errors were detected.

       $self->filename()
	   The filename number the entity was created in.

       $self->info (Text...)
	   Print a informational in a standard format.

       $self->lineno()
	   The line number the entity was created on.

       $self->logger()
	   The class to report errors using, generally a Verilog::Netlist::Logger object.

       $self->userdata (key) =item $self->userdata (key, data)
	   Sets (with two arguments) or retrieves the specified key from an opaque hash.  This may be used to store application data on the
	   specified node.

       $self->warn (Text...)
	   Print a warning in a standard format.

       $self->warnings()
	   Return number of warnings detected.

DISTRIBUTION

       Verilog-Perl is part of the <http://www.veripool.org/> free Verilog EDA software tool suite.  The latest version is available from CPAN and
       from http://www.veripool.org/verilog-perl <http://www.veripool.org/verilog-perl>.

       Copyright 2000-2012 by Wilson Snyder.  This package is free software; you can redistribute it and/or modify it under the terms of either
       the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0.

AUTHORS

       Wilson Snyder <wsnyder@wsnyder.org>

SEE ALSO

       Verilog-Perl, Verilog::Netlist

perl v5.14.2							    2012-05-04						    Netlist::Subclass(3pm)

Linux and UNIX Man Pages

fnf(1) [debian man page]

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