10 More Discussions You Might Find Interesting
1. Shell Programming and Scripting
hi all,
i had the below script
x=`cat input.txt |wc -1`
awk 'NR>1 && NR<'$x' ' input.txt > output.txt
by using above script i am able to remove the head and tail part from the input file and able to append the output to the output.txt but if i run it for second time the output is... (2 Replies)
Discussion started by: hemanthsaikumar
2 Replies
2. Shell Programming and Scripting
Hi/ Hello all Guru here,
I am trying to create script to remove same content from other file, already tested few idea and found that in unix it is limited to sort and uniq. There is many script for removing duplicate content however to delete all same content is non. Need your help and guide .... (7 Replies)
Discussion started by: Mr_47
7 Replies
3. Shell Programming and Scripting
Here is the contents of test.txt
Dependencies Resolved
Changes in packages about to be updated:
ChangeLog for: 1:perl-Archive-Extract-0.38-131.el6_4.x86_64,
- Resolves: #915692 - CVE-2013-1667 (DoS in rehashing code)
Dependencies Resolved
Changes in packages about to be updated:
... (5 Replies)
Discussion started by: ashokvpp
5 Replies
4. Shell Programming and Scripting
Hi All,
I want to remove the content based on the header information .
Please find the example below.
File1.txt
Name|Last|First|Location|DepId|Depname|DepLoc
naga|rr|tion|hyd|1|wer|opr
Nava|ra|tin|gen|2|wera|opra
I have to search for the DepId and remove the data from the... (5 Replies)
Discussion started by: i150371485
5 Replies
5. Shell Programming and Scripting
How can I remove all data that contain domain e.g zzgh@something.com, sdd@something.com.my and gg@something.my in one file? so that i only have data without the domain in the file.
Here is the file structure "test.out"
more test.out
1 zzztop@b.com
1 zzzulll
1 zzzullll@s.com.my
... (4 Replies)
Discussion started by: Mr_47
4 Replies
6. Shell Programming and Scripting
Input
data_10 SSA
data_2 TYUE
data_3 PEOCV
data_6 SSAT
data_21 SSA
data_19 TYUEC
data_14 TYUE
data_15 SSA
data_32 PEOCV
.
.
Desired Output
data_10 SSA
data_2 TYUE
data_3 PEOCV
data_6 SSAT
data_19 TYUEC (9 Replies)
Discussion started by: patrick87
9 Replies
7. Shell Programming and Scripting
Hi, I have a file called fl_list consists of files i have to archive. I want to create a exception parm called except_parm, so if it finds the directory it will not archive these files and remove from fl_list.
$ cat fl_list
/apps/dev/ihub/ready/IA003B/IA003B_Deal_Header_yyyymmdd_hhmmss.txt... (1 Reply)
Discussion started by: k9cheung
1 Replies
8. Shell Programming and Scripting
i am a bit new to shell scripting
i have a file containing
xxxx xx xx
but i want to output the content as
xxxxxxxx.
thus removing the space.
any idea how i can do this (4 Replies)
Discussion started by: blackzinga
4 Replies
9. Shell Programming and Scripting
Hi
I have a big verilog file with multiple modules. Each module begin with the code word 'module <module-name>(ports,...)'
and end with the
'endmodule' keyword.
Could you please suggest the best way to split each of these modules into multiple files?
Thank you for the help.
Example of... (7 Replies)
Discussion started by: return_user
7 Replies
10. Shell Programming and Scripting
hey all, I have a file with records in following format
8-29-2006 13:01:45|ABC|45
8-29-2006 14:23:12|DEF|21
8-30-2006 00:04:57|ABC|34
I want to remove all yesterday records. Can anyone show me how? Thanks! (10 Replies)
Discussion started by: mpang_
10 Replies
VHIER(1p) User Contributed Perl Documentation VHIER(1p)
NAME
vhier - Return all files in a verilog hierarchy using Verilog::Netlist
SYNOPSIS
vhier --help
vhier [verilog_options] [-o filename] [verilog_files.v...]
DESCRIPTION
Vhier reads the Verilog files passed on the command line and outputs a tree of all of the filenames, modules, and cells referenced by that
file.
VERILOG ARGUMENTS
The following arguments are compatible with GCC, VCS and most Verilog programs.
+define+var+value =item -Dvar=value
Defines the given preprocessor symbol.
-F file
Read the specified file, and act as if all text inside it was specified as command line parameters. Any relative paths are relative to
the directory containing the specified file.
-f file
Read the specified file, and act as if all text inside it was specified as command line parameters. Any relative paths are relative to
the current directory.
+incdir+dir =item -Idir
Add the directory to the list of directories that should be searched for include directories or libraries.
+libext+ext+ext...
Specify the extensions that should be used for finding modules. If for example module x is referenced, look in x.ext.
-sv Specifies SystemVerilog language features should be enabled; equivalent to "--language 1800-2009". This option is selected by default,
it exists for compatibility with other simulators.
-y dir
Add the directory to the list of directories that should be searched for include directories or libraries.
VHIER ARGUMENTS
--help
Displays this message and program version and exits.
--o file
Use the given filename for output instead of stdout.
--cells
Show the module name of all cells in top-down order.
--forest
Show "ASCII-art" hierarchy tree of all cells (like ps --forest)
--input-files
Show all input filenames. Copying all of these files should result in only those files needed to represent the entire design.
--instance
Show module instance names.
--language <1364-1995|1364-2001|1364-2005|1800-2005|1800-2009>
Set the language standard for the files. This determines which tokens are signals versus keywords, such as the ever-common "do" (data-
out signal, versus a do-while loop keyword).
--resolve-files
Show resolved filenames passed on the command line. This will convert raw module and filenames without paths to include the library
search path directory. Output filenames will be in the same order as passed on the command line. Unlike --input-files or
--module-files, hierarchy is not traversed.
--module-files
Show all module filenames in top-down order. Child modules will always appear as low as possible, so that reversing the list will
allow bottom-up processing of modules. Unlike input-files, header files are not included.
--modules
Show all module names.
--nomissing
Do not complain about references to missing modules.
--missing-modules
With --nomissing, show all modules that are not found.
--synthesis
Define SYNTHESIS, and ignore text bewteen "ambit", "pragma", "synopsys" or "synthesis" translate_off and translate_on meta comments.
Note using metacomments is discouraged as they have led to silicon bugs (versus ifdef SYNTHESIS); see
<http://www.veripool.org/papers/TenIPEdits_SNUGBos07_paper.pdf>.
--top-module module
Start the report at the specified module name, ignoring all modules that are not the one specified with --top-module or below, and
report an error if the --top-module specified does not exist. Without this option vhier will report all modules, starting at the
module(s) that have no children below them.
Note this option will not change the result of the --input-files list, as the files needed to parse any design are independent of which
modules are used.
--version
Displays program version and exits.
--xml
Create output in XML format.
DISTRIBUTION
Verilog-Perl is part of the <http://www.veripool.org/> free Verilog EDA software tool suite. The latest version is available from CPAN and
from http://www.veripool.org/verilog-perl <http://www.veripool.org/verilog-perl>.
Copyright 2005-2012 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either
the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0.
AUTHORS
Wilson Snyder <wsnyder@wsnyder.org>
SEE ALSO
Verilog-Perl, Verilog::Getopt, Verilog::Preproc, Verilog::Netlist
perl v5.14.2 2012-05-04 VHIER(1p)