echo and exit from makefile


 
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# 1  
Old 04-10-2011
echo and exit from makefile

I have a make file that needs to have allot of options set. Some of these are based on uname and such, some are passed in the call to make.

I need to add an else that will print to the shell and exit under some circumstances.

Code:
   ifeq "$(cmp)" "g44"
      CC++ = g++
   else
      @echo "can't find compiler"
      exit
   endif

This doesn't work, but I hope gives some idea of what I am looking to do. I have searched on echo from make, but I can only find examples of echo as part of a rule.

LMHmedchem
# 2  
Old 04-10-2011
makefiles don't work that way, makefiles are not a shell scripts. Putting exit anywhere won't make it exit because things don't get executed in linear order and only get executed line by line, not as one giant script.

If you want a rule to fail, tell make that it's failed by adding something that returns a nonzero command into one of the rules, like false, to convince make that the rule has failed and stop compilation.
This User Gave Thanks to Corona688 For This Post:
# 3  
Old 04-10-2011
Quote:
Originally Posted by Corona688
makefiles don't work that way, makefiles are not a shell scripts. Putting exit anywhere won't make it exit because things don't get executed in linear order and only get executed line by line, not as one giant script.

If you want a rule to fail, tell make that it's failed by adding something that returns a nonzero command into one of the rules, like false, to convince make that the rule has failed and stop compilation.
I thought I had seen and exit like that in a make file before, I guess I was thinking about something else. So I have to add something to one of the all rules.

LMHmedchem
# 4  
Old 04-10-2011
If you need to do these sort of things it's typically done in a configure script that is run before the makefile is processed. Even if you can get what you need for this requirement by doing some tricky make rules, you are more the likley to encounter further issues down the track.

Probably best to bite the bullet and build a configure script now. A typical install might go something like this:

Code:
$ ./configure --prefix=/usr/local
Can't find compiler - please specify --cmp= with compiler location
 
$./configure --prefix=/usr/local --cmp=/usr/local/bin/gcc
All checks OK - now use make to build XXX
 
$ make

# 5  
Old 04-11-2011
Quote:
Originally Posted by Chubler_XL
If you need to do these sort of things it's typically done in a configure script that is run before the makefile is processed. Even if you can get what you need for this requirement by doing some tricky make rules, you are more the likley to encounter further issues down the track.

Probably best to bite the bullet and build a configure script now. A typical install might go something like this:

Code:
$ ./configure --prefix=/usr/local
Can't find compiler - please specify --cmp= with compiler location
 
$./configure --prefix=/usr/local --cmp=/usr/local/bin/gcc
All checks OK - now use make to build XXX
 
$ make

I have thought about running make from a shell script that would first collect the necessary data, and then define some things in the call to make. I am dealing with an application that I build on many different OSs, in different versions of gcc, and also on different architectures. The number of combinations is a bit daunting, and there are some of them that don't work. I am trying to get away from doing allot of manual editing of the make file, which I think is asking for trouble. I can pass allot of things in when I call make, but doing that manually also has issues.

LMHmedchem
# 6  
Old 04-11-2011
Yep ,sounds like you need to bite the bullet and create a configure script, have a look at autoconf, a lot of the initial hard work can be automated using autoscan.
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