Programming

 +vc <my_file1.c> <my.file2.c> <myfile3.c>.

gcc  -pipe -m32 -O -I/user/vcs_mx/2006.06/include -c ./my_file1.c
gcc  -pipe -m32 -O -I/user/vcs_mx/2006.06/include -c ./my_file2.c
gcc  -pipe -m32 -O -I/user/vcs_mx/2006.06/include -c ./my_file3.c

vcs -mhdl -q -R -l   \
        +incdir+${RTL_INCLUDE}+${RTL_VENCH}+./test.cmd \
        +vc  file_read.c rf_model.c adc_mdl.c \

+vc -gcc <anyoption of gcc compiler>

Useful Compile-Time Options
VCS has other compile-time options that are not specially for DirectC
but you might find them useful when enabling and calling C/C++
functions in your Verilog source code.
-cc
Specifies the C compiler (default is cc in your search path)
-cpp
Specifies the C++ compiler (default is CC in your search path)
-ld
Specifies the linker for final linking to build simv (default is the
same as the C++ compiler)
Note:
Don't specify incompatible C++ compiler and linker (by specifying
-cpp and -ld simultaneously. That may result in compile failure
with unrecognized symbols.
These options may be necessary on the vcs command line. If you
include object files on the command line, you must include the options
to specify which compiler and linker generated these object files.