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gpioiic(4) [netbsd man page]

GPIOIIC(4)						   BSD Kernel Interfaces Manual 						GPIOIIC(4)

gpioiic -- GPIO I2C controller SYNOPSIS
gpioiic* at gpio? offset 0 mask 0x3 flag 0x0 gpioiic* at gpio? iic* at gpioiic? DESCRIPTION
The gpioiic driver allows bit-banging an I2C bus as a master using two GPIO pins. By default the first pin is used as a serial data (SDA) signal and the second as a serial clock (SCL). If the flag locator is set to 0x01, the order of the SDA and SCL signals is reversed. Both GPIO pins must be able to drive an output and the SDA pin must be also able to read an input. The pins can be specified in the kernel configuration with the offset and the mask locators. The offset and mask can also be specified when gpioiic is attached at runtime using the GPIOATTACH ioctl(2) on the gpio(4) device. Each bit in the mask locator defines one pin; the pin number is calculated as an addition of the bit position and the offset locator. For example, offset 17 and mask 0x5 defines pin numbers 17 and 19. SEE ALSO
gpio(4), iic(4), intro(4) HISTORY
The gpioiic driver first appeared in OpenBSD 3.9 and NetBSD 5.0. AUTHORS
The gpioiic driver was written by Alexander Yurchenko <> and was ported to NetBSD by Marc Balmer <>. CAVEATS
A gpioiic device can not be detached from the gpio(4) bus at runtime due to the fact that iic(4) busses can not detach once attached. BSD
October 2, 2011 BSD

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GPIO(4) 						   BSD Kernel Interfaces Manual 						   GPIO(4)

gpiobus -- GPIO bus system SYNOPSIS
To compile these devices into your kernel and use the device hints, place the following lines in your kernel configuration file: device gpio device gpioc device gpioiic device gpioled Additional device entries for the ARM architecture include: device a10_gpio device bcm_gpio device imx51_gpio device lpcgpio device mv_gpio device ti_gpio device gpio_avila device gpio_cambria device zy7_gpio device pxagpio Additional device entries for the MIPS architecture include: device ar71xxx_gpio device octeon_gpio device rt305_gpio Additional device entries for the POWERPC architecture include: device wiigpio device macgpio DESCRIPTION
The gpiobus system provides a simple interface to the GPIO pins that are usually available on embedded architectures and can provide bit banging style devices to the system. The acronym GPIO means ``General-Purpose Input/Output.'' The BUS physically consists of multiple pins that can be configured for input/output, IRQ delivery, SDA/SCL iicbus use, etc. On some embedded architectures (like MIPS), discovery of the bus and configuration of the pins is done via device.hints(5) in the platform's kernel config(5) file. On some others (like ARM), where FDT(4) is used to describe the device tree, the bus discovery is done via the DTS passed to the kernel, being either statically compiled in, or by a variety of ways where the boot loader (or Open Firmware enabled system) passes the DTS blob to the kernel at boot. The following device.hints(5) are only provided by the ar71xx_gpio driver: hint.gpio.%d.pinmask This is a bitmask of pins on the GPIO board that we would like to expose for use to the host operating system. To expose pin 0, 4 and 7, use the bitmask of 10010001 converted to the hexadecimal value 0x0091. hint.gpio.%d.pinon This is a bitmask of pins on the GPIO board that will be set to ON at host start. To set pin 2, 5 and 13 to be set ON at boot, use the bitmask of 10000000010010 converted to the hexadecimal value 0x2012. hint.gpio.function_set hint.gpio.function_clear These are bitmasks of pins that will remap a pin to handle a specific function (USB, UART TX/RX, etc) in the Atheros function registers. This is mainly used to set/clear functions that we need when they are set up or not set up by uBoot. Simply put, each pin of the GPIO interface is connected to an input/output of some device in a system. SEE ALSO
gpioiic(4), gpioled(4), iicbus(4), gpioctl(8) HISTORY
The gpiobus manual page first appeared in FreeBSD 10.0. AUTHORS
This manual page was written by Sean Bruno <>. BSD
November 5, 2013 BSD
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