altera_jtag_uart(4) [freebsd man page]

ALTERA_JTAG_UART(4)					   BSD Kernel Interfaces Manual 				       ALTERA_JTAG_UART(4)

NAME

     altera_jtag_uart -- driver for the Altera JTAG UART Core

SYNOPSIS

     device altera_jtag_uart

     In /boot/device.hints:
     hint.altera_jtag_uart.0.at="nexus0"
     hint.altera_jtag_uart.0.maddr=0x7f000000
     hint.altera_jtag_uart.0.msize=0x40
     hint.altera_jtag_uart.0.irq=0
     hint.altera_jtag_uart.1.at="nexus0"
     hint.altera_jtag_uart.1.maddr=0x7f001000
     hint.altera_jtag_uart.1.msize=0x40

DESCRIPTION

     The altera_jtag_uart device driver provides support for the Altera JTAG UART core, which allows multiple UART-like streams to be carried over
     JTAG.  altera_jtag_uart allows JTAG UART streams to be attached to both the low-level console interface, used for direct kernel input and
     output, and the tty(4) layer, to be used with ttys(5) and login(1).  Sequential Altera JTAG UART devices will appear as ttyu0, ttyu1, etc.

HARDWARE

     Altera JTAG UART devices can be connected to using Altera's nios2-terminal program, with the instance selected using the --instance argument
     on the management host.  altera_jtag_uart supports JTAG UART cores with or without interrupt lines connected; if the irq portion of the
     device.hints entry is omitted, the driver will poll rather than configure interrupts.

SEE ALSO

     login(1), tty(4), ttys(5)

     Altera Embedded Peripherals IP User Guide, Altera Corporation, http://www.altera.com/literature/ug/ug_embedded_ip.pdf, June 2011.

HISTORY

     The altera_jtag_uart device driver first appeared in FreeBSD 10.0.

AUTHORS

     The altera_jtag_uart device driver and this manual page were developed by SRI International and the University of Cambridge Computer Labora-
     tory under DARPA/AFRL contract (FA8750-10-C-0237) (``CTSRD''), as part of the DARPA CRASH research programme.  This device driver was written
     by Robert N. M. Watson.

BUGS

     altera_jtag_uart must dynamically poll to detect when JTAG is present, in order to disable flow control in the event that there is no receiv-
     ing endpoint.  Otherwise, the boot may hang waiting for the JTAG client to be attached, and user processes attached to JTAG UART devices
     might block indefinitely.	However, there is no way to flush the output buffer once JTAG is detected to have disappeared; this means that a
     small amount of stale output data will remain in the output buffer, being displayed by nios2-terminal when it is connected.  Loss of JTAG
     will not generate a hang-up event, as that is rarely the desired behaviour.

     nios2-terminal does not place the client-side TTY in raw mode, and so by default will not pass all control characters through to the UART.

BSD
								  August 18, 2012							       BSD

Check Out this Related Man Page

ALTERA_ATSE(4)						   BSD Kernel Interfaces Manual 					    ALTERA_ATSE(4)

NAME

     atse -- driver for the Altera Triple-Speed Ethernet MegaCore

SYNOPSIS

     device atse
     options ATSE_CFI_HACK

     In /boot/device.hints:
     hint.atse.0.at="nexus0"
     hint.atse.0.maddr=0x7f007000
     hint.atse.0.msize=0x540
     hint.atse.0.rc_irq=1
     hint.atse.0.rx_maddr=0x7f007500
     hint.atse.0.rx_msize=0x8
     hint.atse.0.rxc_maddr=0x7f007520
     hint.atse.0.rxc_msize=0x20
     hint.atse.0.tx_irq=2
     hint.atse.0.tx_maddr=0x7f007400
     hint.atse.0.tx_msize=0x8
     hint.atse.0.txc_maddr=0x7f007420
     hint.atse.0.txc_msize=0x20
     hint.e1000phy.0.at="miibus0"
     hint.e1000phy.0.phyno=0

DESCRIPTION

     The atse device driver provides support for the Altera Triple-Speed Ethernet MegaCore.

HARDWARE

     The current version of the atse driver supports the Ethernet MegaCore as described in version 11.1 of Altera's documentation when the device
     is configured with internal FIFOs.

MAC SELECTION

     The default MAC address for each atse interface is derived from a value stored in cfi(4) flash.  The value is managed by the atsectl(8) util-
     ity.

     Only a single MAC address may be stored in flash.	If the address begins with the Altera prefix 00:07:ed and ends in 00 then up to 16
     addresses will be derived from it by adding the unit number of the interface to the stored address.  For other prefixes, the address will be
     assigned to atse0 and random addresses will be used for other interfaces.	If the stored address is invalid, for example all zero's, multi-
     cast, or the default address shipped on all DE4 boards (00:07:ed:ff:ed:15) then a random address is generated when the device is attached.

SEE ALSO

     miibus(4), netintro(4), ifconfig(8)

     Triple-Speed Ethernet MegaCore Function User Guide, Altera Corporation, November 2011.

HISTORY

     The atse device driver first appeared in FreeBSD 10.0.

AUTHORS

     The atse device driver and this manual page were developed by SRI International and the University of Cambridge Computer Laboratory under
     DARPA/AFRL contract (FA8750-10-C-0237) (``CTSRD''), as part of the DARPA CRASH research programme.  This device driver was written by Bjoern
     A. Zeeb.

BUGS

     The atse driver only supports a single configuration of the MegaCore as installed on the Terasic Technologies Altera DE4 Development and Edu-
     cation Board.

     Only gigabit Ethernet speeds are currently supported.

BSD
								   May 21, 2014 							       BSD

Linux and UNIX Man Pages

altera_jtag_uart(4) [freebsd man page]

Check Out this Related Man Page