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Top Forums UNIX for Beginners Questions & Answers 10gbe ixgbe slow at 420mbyte/s max, p2p lan cat8 1m, tried ethtool and ifconfig options to no avail Post 303045707 by tinfoil3d on Thursday 9th of April 2020 10:52:43 PM
Old 04-09-2020
[SOLVED] 10gbe ixgbe slow at 420mbyte/s max, p2p lan cat8 1m, tried ethtool and ifconfig options

Hey guys, first time dealing with 10gbe.
I have two boxes, one is older with i7 2.8ghz from 2009 generation, pcie 2.0 and I just put the Intel X550T there to make use of absolutely similar but builtin adapter on my newer box with AMD EPYC gen 1.
I'm dling file from tmpfs on either box and never go above 415mbyte/s which is about half of potential bandwidth there, right?
I tried most stuff from kernel . org/doc/ols/2009/ols2009-pages-169-184.pdf with a little improvement from 393mbyte/s to current 415.
that's the result of me setting mtu 9000, txqueuelen 10000.
Also tried this to no improvements over current result: darksideclouds wordpress com/2016/10/10/tuning-10gb-nics-highway-to-hell/
And a few other pages out there on google, most stating same options.
I don't see a 100% load burst on i7 box when I dl file, it's around 10% across the cores. So CPU shouldn't be a bottleneck, cable(it's 1meter cat8, with a nice thick shielding) shouldn't be a bottleneck and ram speed and pcie 2.0 speed shouldn't be.
iperf also reports same speed.
Tried these tests in both directions.
There's gotta be something obvious that I'm missing, right?

Pretty sure it doesn't matter but it's lfs on i7 and debian 10 on epyc, both sharing same sysctl settings and ethtool-controlled options.
lspci -n for it on both computers:
Code:
62:00.0 0200: 8086:1563 (rev 01)

so it's similar device. I bought this particular one for compatibility but didn't expect these issues.

Maybe someone here would suggest something, I'm out of ideas.
TIA
--
solved see my own response

Last edited by tinfoil3d; 04-11-2020 at 08:48 AM.. Reason: solved, it's PCIe lane count, usb3, sata3, 6 disks, one GPU downgraded to x8 and no more space to have x4 on pcie 2.0 mb with max 16 lanes i7 CPU
 

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CZ(4)							   BSD Kernel Interfaces Manual 						     CZ(4)

NAME
cz -- Cyclades-Z series multi-port serial adapter device driver SYNOPSIS
cz* at pci? dev ? function ? DESCRIPTION
The cz device driver supports the Cyclades-Z series of multi-port serial adapters. The Cyclades-Z is an intelligent serial controller com- prising: o PLX9060ES PCI bus interface o Xilinx XC5204 FPGA o IDT R3052 MIPS CPU The MIPS CPU runs firmware provided by the device driver. Communication with the MIPS is performed by modifying data structures located in board local RAM or host RAM. The Cyclades-Z comes in three basic flavors: o Cyclades-8Zo rev. 1 -- This is an older 8-port board with no FPGA. The serial ports are provided by an octopus cable. o Cyclades-8Zo rev. 2 -- This is the newer 8-port board. The serial ports are provided by an octopus cable. o Cyclades-Ze -- This is the expandable version of the Cyclades-Z. It uses an HD-50 SCSI cable to connect the board to a 1U rack mountable serial expansion box. Each box has 16 RJ45 serial ports, and up to 4 boxes may be chained together, for a total of 64 ports. Boxes 3 and 4 require their own external power supply, otherwise the firmware will refuse to start (as it cannot communi- cate with the UARTs in those boxes). The Cyclades-Z has several features to improve performance under high serial I/O load: o The board may operate in interrupt-driven mode or polled mode to reduce interrupt load. o Each channel has a large input and output buffer. o Each channel may be programmed to generate an interrupt based on reception of a specific character, e.g. a PPP End-Of-Frame charac- ter. o The MIPS CPU on the board performs all flow-control handling. FILES
/dev/ttyCZnnnn -- dial-in (normal) TTY device /dev/dtyCZnnnn -- dial-out TTY device SEE ALSO
pci(4), termios(4), tty(4) HISTORY
The cz driver first appeared in NetBSD 1.5. AUTHORS
The cz driver was written by Jason R. Thorpe <thorpej@zembu.com> and Bill Studenmund <wrstuden@zembu.com> of Zembu Labs, Inc. BUGS
The cz driver does not currently implement communication via host RAM. While this may improve performance by reducing the number of PCI mem- ory space read/write cycles, it is not straightforward to implement with the current bus_dma(9) API. Interrupt mode has not been tested. There is no support for reading or writing the EEPROM connected to the PLX PCI bus controller. BSD
May 17, 2000 BSD
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