I have a big makefile that I am trying to get my head around, this line is what is confusing me.
I know roughly the purpose of LDFLAGS, but I struggle following the chain of variables in this linker flag expression. It seems like there is unnecessary repetition and that confuses me slightly. I need to modify that makefile to include shared library that the manufacturer of the embedded system has made. The line below is what is only provided in the software manual for that system,
I'd like to include lGSM_Module in the above LDFLAGS variable. I have tried this, but successfully.
I have this program which has lots of source files in the directories
src
src/dir1
src/dir2
src/dir3... and so on
I am trying to understand the following Makefile:
CC = gcc
CFLAGS= -g -c -D_REENTRANT
SOURCES = src/main.c src/dir1/a.c src/dir1/b.c src/dir2/x.c src/dir2/y.c ...and so on... (5 Replies)
Hi, I'm trying to run the module load command in a Makefile and i'm getting the following error:
make: module: command not found
Why is this? Is there any way to run this command in a Makefile?
NOTE: command - module load msjava/sunjdk/1.5.0 works fine outside of the Makefile (2 Replies)
I am able to 'Make' some of projects's modules using GNU's make except one where it throws me the following error
gmake -f Makefile
/bin/sh: syntax error at line 1: `if' unexpected
gmake: *** Error 2
I am sure it has nothing to do with the Makefile as there is no 'if' in the first... (1 Reply)
I have 2 libraries in 2 different directories that I build with Makefiles.
library B depends on library A. If I modify a .cpp file in library A and run lib B's Makefile can I have B's makefile to automatically rebuild library A?
I am now rebuilding A, followed by B... but I'd like B to... (0 Replies)
Use and complete the template provided. The entire template must be completed. If you don't, your post may be deleted!
1. The problem statement, all variables and given/known data:
Basically, the prompt is make a makefile with various sub makefiles in their respective subdirectories. All code... (1 Reply)
Hi,
I am creating a program with the C language that simulates the WC command in Unix. My program needs to count lines, bytes and words. I have not added the code to count bytes and words yet. I am having trouble understanding what the file option/flag '-' does. I can not visualize how it moves... (1 Reply)
Hello,
I have to write makefile which supports specific targets and I have to do the following things:
- A variable T determines whether the function is executed 1 or 2
- A variable N determines which size will be executed
e.g. it must be read from the command line "make 1500" where 1... (0 Replies)
Hi all,
I'm reading the GNU Make book I cannot understand the following syntax from the book.
objects = foo.o bar.o
all : $(objects)
$(objects) : %.o : %.c
$(CC) -c $(CFLAGS) $< -o $@
If I run: make, I get the output:
cc -c foo.c
cc -o foo foo.o
I think I... (3 Replies)
gccmakedep(1) General Commands Manual gccmakedep(1)NAME
gccmakedep - create dependencies in makefiles using 'gcc -M'
SYNOPSIS
gccmakedep [ -sseparator ] [ -fmakefile ] [ -a ] [ -- options -- ] sourcefile ...
DESCRIPTION
The gccmakedep program calls 'gcc -M' to output makefile rules describing the dependencies of each sourcefile, so that make(1) knows which
object files must be recompiled when a dependency has changed.
By default, gccmakedep places its output in the file named makefile if it exists, otherwise Makefile. An alternate makefile may be speci-
fied with the -f option. It first searches the makefile for a line beginning with
# DO NOT DELETE
or one provided with the -s option, as a delimiter for the dependency output. If it finds it, it will delete everything following this up
to the end of the makefile and put the output after this line. If it doesn't find it, the program will append the string to the makefile
and place the output after that.
EXAMPLE
Normally, gccmakedep will be used in a makefile target so that typing 'make depend' will bring the dependencies up to date for the make-
file. For example,
SRCS = file1.c file2.c ...
CFLAGS = -O -DHACK -I../foobar -xyz
depend:
gccmakedep -- $(CFLAGS) -- $(SRCS)
OPTIONS
The program will ignore any option that it does not understand, so you may use the same arguments that you would for gcc(1), including -D
and -U options to define and undefine symbols and -I to set the include path.
-a Append the dependencies to the file instead of replacing existing dependencies.
-fmakefile
Filename. This allows you to specify an alternate makefile in which gccmakedep can place its output. Specifying "-" as the file
name (that is, -f-) sends the output to standard output instead of modifying an existing file.
-sstring
Starting string delimiter. This option permits you to specify a different string for gccmakedep to look for in the makefile. The
default is "# DO NOT DELETE".
-- options --
If gccmakedep encounters a double hyphen (--) in the argument list, then any unrecognized arguments following it will be silently
ignored. A second double hyphen terminates this special treatment. In this way, gccmakedep can be made to safely ignore esoteric
compiler arguments that might normally be found in a CFLAGS make macro (see the EXAMPLE section above). -D, -I, and -U options
appearing between the pair of double hyphens are still processed normally.
SEE ALSO gcc(1), make(1), makedepend(1).
AUTHOR
The version of the gccmakedep included in this X.Org Foundation release was originally written by the XFree86 Project based on code sup-
plied by Hongjiu Lu.
Colin Watson wrote this manual page, originally for the Debian Project, based partly on the manual page for makedepend(1).
X Version 11 gccmakedep 1.0.2 gccmakedep(1)