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Operating Systems Solaris SunOS 5.5.1 usage of Makefile command in make file Post 302971839 by rajujayanthy on Tuesday 26th of April 2016 08:32:16 AM
Old 04-26-2016
SunOS 5.5.1 usage of Makefile command in make file

I am new to Solaris and compilation using make files.
I have a code base which is organized into different folders. At the root folder is a master make file and in the sub directories, there are make files for that particular folder.

In the make files present in subdirectories, I am seeing that "Makefile" is being used as a command for generating .obj files. For e.g.
Code:
 abc.obj : abc.asm \
 ../kernal/xxx.def \
 ../kernal/yyy.def \
 ../kernal/zzz.def \
 ../kernal/queue.def \
 Makefile \
 aaa.def \
 bbb.asm \
 ccc.asm \
 ddd.mac

Some other line
Code:
 abc.obj : abc.asm Makefile $(BB_INCS) xxx.def

Below are my questions.

1. Why is "Makefile" being used as a command? What does it signify? It is not defined anywhere in any other make file also.
2. What is a .mac file in Solaris? what is it's purpose?
3. What is the use of .def file in SOlaris? What is it's purpose?
 

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MAKE(1) 						      General Commands Manual							   MAKE(1)

NAME
make - a program for maintaining large programs SYNOPSIS
make [-f file] [-iknpqrst] [option] ... [target] OPTIONS
-f Use file as the makefile -i Ignore status returned by commands -k On error, skip to next command -n Report, but do not execute -p Print macros and targets -q Question up-to-dateness of target -r Rule inhibit; do not use default rules -s Silent mode -t Touch files instead of making them EXAMPLES
make kernel # Make kernel up to date make -n -f mfile # Tell what needs to be done DESCRIPTION
Make is a program that is normally used for developing large programs consisting of multiple files. It keeps track of which object files depend on which source and header files. When called, it does the minimum amount of recompilation to bring the target file up to date. The file dependencies are expected in makefile or Makefile , unless another file is specified with -f. Make has some default rules built in, for example, it knows how to make .s files from .c files. Here is a sample makefile . d=/user/ast # d is a macro program: head.s tail.s# program depends on these cc -o program head.s tail.s# tells how to make program echo Program done. # announce completion head.s: $d/def.h head.c # head.s depends on these tail.s: $d/var.h tail.c # tail.s depends on these A complete description of make would require too much space here. Many books on UNIX discuss make . Study the numerous Makefiles in the MINIX source tree for examples. SEE ALSO
cc(1). MAKE(1)
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