SunOS 5.5.1 usage of Makefile command in make file
I am new to Solaris and compilation using make files.
I have a code base which is organized into different folders. At the root folder is a master make file and in the sub directories, there are make files for that particular folder.
In the make files present in subdirectories, I am seeing that "Makefile" is being used as a command for generating .obj files. For e.g.
Some other line
Below are my questions.
1. Why is "Makefile" being used as a command? What does it signify? It is not defined anywhere in any other make file also.
2. What is a .mac file in Solaris? what is it's purpose?
3. What is the use of .def file in SOlaris? What is it's purpose?
Hi,
This stems from the following thread https://www.unix.com/showthread.php?t=18299
I have a makefile which makes either executables or a shared library.
i.e. make -f unix.mak will create the executables and
make -f unix.mak libolsv will create the shared library.
Since these have to be... (4 Replies)
I have compiled binary file using "cc" on SunOS 5.8 and the same binary file i have copied to SunOS 5.9 and it is giving me core dump error.I want to know whether migration of compiled code from lower version to higer version created this problem. how can i solve this problem.I am pasting the core... (1 Reply)
I am using a SunOS to compile a project. The Makefile contains commands "$(MAKE) -C $$dir". However, in "man make" there is no -C option. I tried using MAKE=gmake but it failed too. My questions:
1. The make options for this SunOS is different from the gnu make options. Is it because of the... (4 Replies)
Hello everybody,
Currently I'm learning how to build projects (C programming) with GNU make. I have a problem with one Makefile and I would appreciate if you could kindly give me a hand. Here is the environment:
OS: Redhat linux 5
compiler: gcc (GCC) 4.1.2 20080704 (Red Hat 4.1.2-44)... (2 Replies)
ok, so i'm trying to write a shell script (not perl) that monitors memory usage on a server. but i'm confused as to what fields exactly determines that yes, memory is low on a particular server.
it sounds simple enough, but it really isn't. what do I look for in the field below?
... (1 Reply)
I am trying to create a makefile to build a program and am getting the following error:
make -f tsimplex.mk
make: *** No rule to make target `/main/tsimplex_main.cpp', needed by `tsimplex_main.o'. Stop.
OPSYS = $(shell uname -s )
TARGET = tsimplex
ROOTDIR = ../../..
GTSDIR =... (1 Reply)
I've created a tag in the makefile:
mytag: $(shell ${PWD}/script.sh)
When i do: make clean - the script is executed
When i perform make or make mytag the script is again executed with the output:
make: Nothing to be done for mytag
What i want ?
I want script.sh to be executed only... (0 Replies)
SOLVED NOW
Solution:
Using bmake was the key. Ran into some few errors when using the compilers and the trick here was to first install the pkg system/header and then assign the working compiler in command line like this:
bmake CC=/path/to/relevant/gcc CXX=/path/to/relevant/g++... (0 Replies)
Hello,
My makefiles are set up to generate an environment specific build directory based on the local configuration and some values passed to make. It generally looks like,
# compilers, may be passed to make
CC++ = g++
FCOMP = gfortran
# version of program, may be passed to make
ver =... (4 Replies)
Discussion started by: LMHmedchem
4 Replies
LEARN ABOUT MINIX
make
MAKE(1) General Commands Manual MAKE(1)NAME
make - a program for maintaining large programs
SYNOPSIS
make [-f file] [-iknpqrst] [option] ... [target]
OPTIONS -f Use file as the makefile
-i Ignore status returned by commands
-k On error, skip to next command
-n Report, but do not execute
-p Print macros and targets
-q Question up-to-dateness of target
-r Rule inhibit; do not use default rules
-s Silent mode
-t Touch files instead of making them
EXAMPLES
make kernel # Make kernel up to date
make -n -f mfile # Tell what needs to be done
DESCRIPTION
Make is a program that is normally used for developing large programs consisting of multiple files. It keeps track of which object files
depend on which source and header files. When called, it does the minimum amount of recompilation to bring the target file up to date.
The file dependencies are expected in makefile or Makefile , unless another file is specified with -f. Make has some default rules built
in, for example, it knows how to make .s files from .c files. Here is a sample makefile .
d=/user/ast # d is a macro
program: head.s tail.s# program depends on these
cc -o program head.s tail.s# tells how to make program
echo Program done. # announce completion
head.s: $d/def.h head.c # head.s depends on these
tail.s: $d/var.h tail.c # tail.s depends on these
A complete description of make would require too much space here. Many books on UNIX discuss make . Study the numerous Makefiles in the
MINIX source tree for examples.
SEE ALSO cc(1).
MAKE(1)