Sponsored Content
Top Forums Programming Makefile No rule to make target Post 302887420 by Corona688 on Friday 7th of February 2014 11:20:30 AM
Old 02-07-2014
Your makefile has the rule tsimplex_main.o : $(MAINDIR)/tsimplex_main.cpp but tsimplex_main.cpp is either missing or not where the makefile expected it to be. make's usual reaction when it can't find a file is to try and create it, but it has no rule to make a .cpp file from scratch, so it quits.
 

10 More Discussions You Might Find Interesting

1. UNIX for Dummies Questions & Answers

make and clean in a single rule in the makefile.

Hi, This stems from the following thread https://www.unix.com/showthread.php?t=18299 I have a makefile which makes either executables or a shared library. i.e. make -f unix.mak will create the executables and make -f unix.mak libolsv will create the shared library. Since these have to be... (4 Replies)
Discussion started by: vino
4 Replies

2. Solaris

Makefile:57: *** multiple target patterns. Stop.

Hi, I am getting the following error while building on Solaris 64 , while I am trying to build. Error Snippet :- ---------------------- Makefile:57: *** multiple target patterns. Stop. make: Leaving directory `/work1/patch/vds6053sun64o/vobs/jvi' make: *** Error 2 make: Leaving directory... (0 Replies)
Discussion started by: nileshborate
0 Replies

3. Shell Programming and Scripting

Makefile debug target

Hello, I'm having a problem with a makefile script i'm trying to write. I want to compile a C++ program in two possible ways: "make" (default target, main) and "make debug". When i supply the debug target, exactly the same as main should be built, but then with the DEBUG flag (-g -D... (2 Replies)
Discussion started by: StevenR
2 Replies

4. Programming

Makefile: multiple target variable substitution

Greetings! Basically, I would like to properly handle this with gnu make: alltools: my_tool mysecond_tool mythird_tool etc_tool %_tool: dir1/%_tool.vf dir2/%_tool/subdir2/%_tool.ver <tab>@echo done %.vf: <tab>RUN_VF $* %.ver: <tab>RUN_VER $* So, if I were to do something like:... (0 Replies)
Discussion started by: Harlinator
0 Replies

5. Shell Programming and Scripting

Makefile rule being skipped

I can't seem to get a rule in my Makefile to ever run... even if I change the rule to force make to re-enter the rule, or if I change the dependent files the rule depends on. Any ideas why the second rule is being ignored here? #MAKEFILES = $(DIRS:%=$(ROOT)/%/Makefile) #$(MAKEFILES):... (0 Replies)
Discussion started by: foureightyeast
0 Replies

6. Programming

compile fails in linux ... "No rule to make target" ... HELP

hello all, attached you can find a tool (written in C) that i really need to make it compile under linux i am able to compile and run it successfully in mac os x, but in linux the compilation fails the only thing that i did so far is to change the following #include <sys/malloc.h> to... (13 Replies)
Discussion started by: OneDreamCloser
13 Replies

7. Programming

Issue with make, no rule to make target etc.

I have been trying to split up my src directory to clear out files that are not re-compiled very often. Now I have the following setup in my trunk, trunk/bld trunk/src/ trunk/src/src_server trunk/makefile.linux In the make file, I have compile rules SOURCELOC = src # compile src c++... (4 Replies)
Discussion started by: LMHmedchem
4 Replies

8. Shell Programming and Scripting

MakeFile Backup Target

Goal: I'm trying to create a PHONY target inside my Makefile so that when I run the command "make backup", It will move all the files that end in "~" into the specified backup folder. Here is my code currently, and I'll explain the problem after: .PHONY: backup backup: @mkdir -p... (2 Replies)
Discussion started by: Xploit
2 Replies

9. UNIX for Dummies Questions & Answers

Defining a new suffix rule in a Makefile

Hi everybody, I have a Makefile where a single suffix rule is defined: .SUFFIXES: .cpp .cpp.o: ${CXX} ${CXXFLAGS} -c -o $@ $< And I'd like to create another where an additional flag is added to compile in SMP. Right now, I have to do it like this: interface-smp.o:... (2 Replies)
Discussion started by: Zel2008
2 Replies

10. Shell Programming and Scripting

Default rule to be executed in makefile

Hi all, I want to know the entry point (default rule to be executed) in a makefile once all defined variables are evaluated. I do not have all: in my makefile and I give "make" without any parameter in command line. thanks........ (3 Replies)
Discussion started by: useless79
3 Replies
ccmakedep(1)						      General Commands Manual						      ccmakedep(1)

NAME
ccmakedep - create dependencies in makefiles using a C compiler SYNOPSIS
ccmakedep [ cpp-flags ] [ -wwidth ] [ -smagic-string ] [ -fmakefile ] [ -oobject-suffix ] [ -v ] [ -a ] [ -cccompiler ] [ -- options -- ] sourcefile ... DESCRIPTION
The ccmakedep program calls a C compiler to preprocess each sourcefile, and uses the output to construct makefile rules describing their dependencies. These rules instruct make(1) on which object files must be recompiled when a dependency has changed. By default, ccmakedep places its output in the file named makefile if it exists, otherwise Makefile. An alternate makefile may be speci- fied with the -f option. It first searches the makefile for a line beginning with # DO NOT DELETE or one provided with the -s option, as a delimiter for the dependency output. If it finds it, it will delete everything following this up to the end of the makefile and put the output after this line. If it doesn't find it, the program will append the string to the makefile and place the output after that. EXAMPLE
Normally, ccmakedep will be used in a makefile target so that typing 'make depend' will bring the dependencies up to date for the makefile. For example, SRCS = file1.c file2.c ... CFLAGS = -O -DHACK -I../foobar -xyz depend: ccmakedep -- $(CFLAGS) -- $(SRCS) OPTIONS
The program will ignore any option that it does not understand, so you may use the same arguments that you would for cc(1), including -D and -U options to define and undefine symbols and -I to set the include path. -a Append the dependencies to the file instead of replacing existing dependencies. -cccompiler Use this compiler to generate dependencies. -fmakefile Filename. This allows you to specify an alternate makefile in which ccmakedep can place its output. Specifying "-" as the file name (that is, -f-) sends the output to standard output instead of modifying an existing file. -sstring Starting string delimiter. This option permits you to specify a different string for ccmakedep to look for in the makefile. The default is "# DO NOT DELETE". -v Be verbose: display the C compiler command before running it. -- options -- If ccmakedep encounters a double hyphen (--) in the argument list, then any unrecognized arguments following it will be silently ignored. A second double hyphen terminates this special treatment. In this way, ccmakedep can be made to safely ignore esoteric compiler arguments that might normally be found in a CFLAGS make macro (see the EXAMPLE section above). -D, -I, and -U options appearing between the pair of double hyphens are still processed normally. SEE ALSO
cc(1), make(1), makedepend(1), ccmakedep(1). AUTHOR
ccmakedep was written by the X Consortium. Colin Watson wrote this manual page, originally for the Debian Project, based partly on the manual page for makedepend(1). X Version 11 imake 1.0.5 ccmakedep(1)
All times are GMT -4. The time now is 01:52 PM.
Unix & Linux Forums Content Copyright 1993-2022. All Rights Reserved.
Privacy Policy