You need a generalized rule for how to get from a "source" file to an "object" file. If your source files carry the extension ".src" and your objects the extension ".obj" this would be:
Now you only need a special variable which contains only the file name which triggered the rule to use in the action part - and fortunately there is such a thing: "$<". A possible rule would look like:
If the rule is triggered by the file "foo.src" the command executed would be:
You might want to read the man page of the make-utility to learn more about the various special variables you can use. For instance, there is also a variable for the file name that will be the target of the rule: "$@".
C compilers per default write a file "a.out" instead of naming the object like the source file only with the extension replaced by ".obj". You would have to explicitly tell the compiler which name it should use for its output file with the "-o" option if you do not want this default behavior. This is what "$@" is for:
I am sure you will be able to adapt this to your needs with careful study of the man page.
I am attempting to set-up a Makefile to use for a new system on a Sun Unix machine.
I am new to creating Makefiles. I am trying to start simply by compiling a program. I am getting the following error message but an uncertain what 'Error Code 1' is. Is there a web site with Error Codes... (1 Reply)
I'm trying to do string replacement with a Makefile and this is my scenario:
Inside file "fileA", I have "#include<text>" statements and I want to replace it with the text inside a file called "params". I wish to perform this task using Makefiles. I've tried using m4 but that only works if... (1 Reply)
At my company, we build some stuff using a makefile. While the makefile script is running, a developer may check in a newer version of a source file. The problem is, when we next run the make command, the target file isn't rebuilt, because the date of the target is after the dependency.
Any... (1 Reply)
Hi All
I need to parse the target
something like:
ifeq '$@' 'first'
echo 1 $@
endif
ifeq '$@' 'second'
echo 2 $@
endif
The thing is to be able compare the target string to any string and then do the commands
Thanks a lot
ziv (0 Replies)
Hi all,
I've a makefile which has this line:
@touch $@
I know $@ is for representing the target. But I don't know what's the @ preceding the touch.
Can anyone help me?
Thanks in advance. (4 Replies)
Hello, I'm trying to use the make command with a makefile I've made for an assignment. The professor supplied the code and I've copied it into a new file. I made sure to place the tabs in the correct spaces, however when I try to execute it in UNIX I get:
"make: Fatal error in reader:... (5 Replies)
Hi all,
In a makefile I would like to grab the first line of a given parameter file using ‘head' and assign it to a variable, how do I do this?
I've got a simple makefile but it does not work?
#! /bin/ksh
...
.sqc.c:
db2prep $*.sqc bindfile
if ] DB2_PARM=`/usr/bin/head -1 $*.prm`; fi... (2 Replies)
Hi,
I wanted to know whether there is any way to specify in a makefile how to compile sources from a directory directly by giving the directory path name instead of mentioning each and every source file name.
Regards,
Anil (1 Reply)
Hi!
I've got a build process where scripts create multiple targets from their sources. But here I'm running into a conceptual problem of GNU make: If one has multiple targets in a dependency, make applies the rules once for every target that is out of sync - which is correct for normal... (3 Replies)
hello, I'm trying to create a makefile to run multiple c files. I am able to run one c file only with the code I have when I tried to run 2 or more c files I'm not able. here is my code
# $Source: /home/hectormasencio/make/Makefile,v $
# $Date: 2012/11/27 11:35:30 $
CC= gcc
OBJS= temp.o... (3 Replies)
Discussion started by: Hector M.
3 Replies
LEARN ABOUT MINIX
make
MAKE(1) General Commands Manual MAKE(1)NAME
make - a program for maintaining large programs
SYNOPSIS
make [-f file] [-iknpqrst] [option] ... [target]
OPTIONS -f Use file as the makefile
-i Ignore status returned by commands
-k On error, skip to next command
-n Report, but do not execute
-p Print macros and targets
-q Question up-to-dateness of target
-r Rule inhibit; do not use default rules
-s Silent mode
-t Touch files instead of making them
EXAMPLES
make kernel # Make kernel up to date
make -n -f mfile # Tell what needs to be done
DESCRIPTION
Make is a program that is normally used for developing large programs consisting of multiple files. It keeps track of which object files
depend on which source and header files. When called, it does the minimum amount of recompilation to bring the target file up to date.
The file dependencies are expected in makefile or Makefile , unless another file is specified with -f. Make has some default rules built
in, for example, it knows how to make .s files from .c files. Here is a sample makefile .
d=/user/ast # d is a macro
program: head.s tail.s# program depends on these
cc -o program head.s tail.s# tells how to make program
echo Program done. # announce completion
head.s: $d/def.h head.c # head.s depends on these
tail.s: $d/var.h tail.c # tail.s depends on these
A complete description of make would require too much space here. Many books on UNIX discuss make . Study the numerous Makefiles in the
MINIX source tree for examples.
SEE ALSO cc(1).
MAKE(1)