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Top Forums Shell Programming and Scripting Question in creating targets in makefile Post 302843986 by bakunin on Friday 16th of August 2013 03:49:29 AM
Old 08-16-2013
You need a generalized rule for how to get from a "source" file to an "object" file. If your source files carry the extension ".src" and your objects the extension ".obj" this would be:

Code:
.src.obj
               <actions here>

Now you only need a special variable which contains only the file name which triggered the rule to use in the action part - and fortunately there is such a thing: "$<". A possible rule would look like:

Code:
COMPILE=/path/to/compiler
FLAGS=-a -b -c
.src.obj
               $(COMPILE) $(FLAGS) $<

If the rule is triggered by the file "foo.src" the command executed would be:

Code:
/path/to/compiler -a -b -c foo.src

You might want to read the man page of the make-utility to learn more about the various special variables you can use. For instance, there is also a variable for the file name that will be the target of the rule: "$@".

C compilers per default write a file "a.out" instead of naming the object like the source file only with the extension replaced by ".obj". You would have to explicitly tell the compiler which name it should use for its output file with the "-o" option if you do not want this default behavior. This is what "$@" is for:

Code:
COMPILE=/path/to/compiler
FLAGS=-a -b -c
.src.obj
               $(COMPILE) $(FLAGS) $< -o $@

I am sure you will be able to adapt this to your needs with careful study of the man page.

I hope this helps.

bakunin
This User Gave Thanks to bakunin For This Post:
 

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MAKE(1) 						      General Commands Manual							   MAKE(1)

NAME
make - a program for maintaining large programs SYNOPSIS
make [-f file] [-iknpqrst] [option] ... [target] OPTIONS
-f Use file as the makefile -i Ignore status returned by commands -k On error, skip to next command -n Report, but do not execute -p Print macros and targets -q Question up-to-dateness of target -r Rule inhibit; do not use default rules -s Silent mode -t Touch files instead of making them EXAMPLES
make kernel # Make kernel up to date make -n -f mfile # Tell what needs to be done DESCRIPTION
Make is a program that is normally used for developing large programs consisting of multiple files. It keeps track of which object files depend on which source and header files. When called, it does the minimum amount of recompilation to bring the target file up to date. The file dependencies are expected in makefile or Makefile , unless another file is specified with -f. Make has some default rules built in, for example, it knows how to make .s files from .c files. Here is a sample makefile . d=/user/ast # d is a macro program: head.s tail.s# program depends on these cc -o program head.s tail.s# tells how to make program echo Program done. # announce completion head.s: $d/def.h head.c # head.s depends on these tail.s: $d/var.h tail.c # tail.s depends on these A complete description of make would require too much space here. Many books on UNIX discuss make . Study the numerous Makefiles in the MINIX source tree for examples. SEE ALSO
cc(1). MAKE(1)
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