I have a question related to makefile. I'm new to makefile and I'm in the process of writing a makefile for my RBT build. I have multiple source files and when I compile them I will get multiple object files (one object file for each source file). I'm having problem in creating a target for each object file with out hardcoding the object file names. I read the list of source file names from another make file. Assume the variable SRC_NAMES contains list of source file names (say test1.c test2.c test3.c). Now I want to create target for each objects for it (say test1.obj test2.obj test3.obj). Currently I have written some thing like below,
This is not working. Since OBJS_LIST contains many object names, compilation action is repeated for many times for the target $(OBJS_LIST). My question is how to split the obj target into multiple targets without hard-coding the target obj names?
Thanks,
Anand
Last edited by Anand Venkatesa; 08-16-2013 at 03:46 AM..
Reason: Trivial Change in Title
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Hi All
I need to parse the target
something like:
ifeq '$@' 'first'
echo 1 $@
endif
ifeq '$@' 'second'
echo 2 $@
endif
The thing is to be able compare the target string to any string and then do the commands
Thanks a lot
ziv (0 Replies)
Hi all,
I've a makefile which has this line:
@touch $@
I know $@ is for representing the target. But I don't know what's the @ preceding the touch.
Can anyone help me?
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"make: Fatal error in reader:... (5 Replies)
Hi all,
In a makefile I would like to grab the first line of a given parameter file using ‘head' and assign it to a variable, how do I do this?
I've got a simple makefile but it does not work?
#! /bin/ksh
...
.sqc.c:
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Hi,
I wanted to know whether there is any way to specify in a makefile how to compile sources from a directory directly by giving the directory path name instead of mentioning each and every source file name.
Regards,
Anil (1 Reply)
Hi!
I've got a build process where scripts create multiple targets from their sources. But here I'm running into a conceptual problem of GNU make: If one has multiple targets in a dependency, make applies the rules once for every target that is out of sync - which is correct for normal... (3 Replies)
hello, I'm trying to create a makefile to run multiple c files. I am able to run one c file only with the code I have when I tried to run 2 or more c files I'm not able. here is my code
# $Source: /home/hectormasencio/make/Makefile,v $
# $Date: 2012/11/27 11:35:30 $
CC= gcc
OBJS= temp.o... (3 Replies)
Discussion started by: Hector M.
3 Replies
LEARN ABOUT XFREE86
ccmakedep
ccmakedep(1) General Commands Manual ccmakedep(1)NAME
ccmakedep - create dependencies in makefiles using a C compiler
SYNOPSIS
ccmakedep [ cpp-flags ] [ -wwidth ] [ -smagic-string ] [ -fmakefile ] [ -oobject-suffix ] [ -v ] [ -a ] [ -cccompiler ] [ -- options -- ]
sourcefile ...
DESCRIPTION
The ccmakedep program calls a C compiler to preprocess each sourcefile, and uses the output to construct makefile rules describing their
dependencies. These rules instruct make(1) on which object files must be recompiled when a dependency has changed.
By default, ccmakedep places its output in the file named makefile if it exists, otherwise Makefile. An alternate makefile may be speci-
fied with the -f option. It first searches the makefile for a line beginning with
# DO NOT DELETE
or one provided with the -s option, as a delimiter for the dependency output. If it finds it, it will delete everything following this up
to the end of the makefile and put the output after this line. If it doesn't find it, the program will append the string to the makefile
and place the output after that.
EXAMPLE
Normally, ccmakedep will be used in a makefile target so that typing 'make depend' will bring the dependencies up to date for the makefile.
For example,
SRCS = file1.c file2.c ...
CFLAGS = -O -DHACK -I../foobar -xyz
depend:
ccmakedep -- $(CFLAGS) -- $(SRCS)
OPTIONS
The program will ignore any option that it does not understand, so you may use the same arguments that you would for cc(1), including -D
and -U options to define and undefine symbols and -I to set the include path.
-a Append the dependencies to the file instead of replacing existing dependencies.
-cccompiler
Use this compiler to generate dependencies.
-fmakefile
Filename. This allows you to specify an alternate makefile in which ccmakedep can place its output. Specifying "-" as the file
name (that is, -f-) sends the output to standard output instead of modifying an existing file.
-sstring
Starting string delimiter. This option permits you to specify a different string for ccmakedep to look for in the makefile. The
default is "# DO NOT DELETE".
-v Be verbose: display the C compiler command before running it.
-- options --
If ccmakedep encounters a double hyphen (--) in the argument list, then any unrecognized arguments following it will be silently
ignored. A second double hyphen terminates this special treatment. In this way, ccmakedep can be made to safely ignore esoteric
compiler arguments that might normally be found in a CFLAGS make macro (see the EXAMPLE section above). -D, -I, and -U options
appearing between the pair of double hyphens are still processed normally.
SEE ALSO cc(1), make(1), makedepend(1), ccmakedep(1).
AUTHOR
ccmakedep was written by the X Consortium.
Colin Watson wrote this manual page, originally for the Debian Project, based partly on the manual page for makedepend(1).
XFree86 Version 4.7.0 ccmakedep(1)