Originally Posted by bakunin

The errors are to take quite literally:

You execute "make" with the arguments "foo" "." "make" and "$(EXE)".

The first error is from the shell, because "$(EXE)" means run command "EXE" in a subshell and put its output here. The shell thinks that the rest of the command depends on what EXE might output and therefor execute it first - as there is no "EXE, this fails.

Next, "make" is executed and takes the argument: "foo". For "foo" exists a target to make and "make" does try to make it but notices that it has already done so and in the meantime "foo" hasn't changed - so it tells you that "foo" is already up to date. Next make tries to "make .". As "." is the current directory and there is no rule in your makefile describing how to make "." "make" tells you so. Finally it tries to make "make", which would be (like ".") a perfectly valid target to make - IF it would exist in your makefile. As it doesn't, "make" tells you the same as with ".": it can't make it, because you haven't told it how.

But instead of writing a long-winded make-exegesis, i could probably tell you what you need to know, so: what exactly do you want to achieve? Have you ever used a makefile and know its purposes? Its syntax?

I hope this helps.

bakunin