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Full Discussion: What is a CPU with 2C/4T?
Special Forums Hardware What is a CPU with 2C/4T? Post 302462907 by DGPickett on Friday 15th of October 2010 09:29:52 AM
Old 10-15-2010
Intel Hyperthreading shares internal resources of one core between 2 threads. I do not recall, but it might be call hyperthreading not hyperprocessing because the VM translation is shared, so they must be 2 threads of the same process (also less security worry that way). Google the wiki. AnandTech does in-depth CPU analysis and benchmarking.

This is a pretty wide ranging subject. One new chip lowers power and speed on idle cores and raises on remaining busy cores, Turbo Boost as I recall. Otherwise, all things being equal, CPUs on different RAM/motherboard (clustered) run faster than on same RAM/motherboard (SMP), which in turn run faster than on same chip, l2 cache and FSB, which in turn run faster than when hyperthread-sharing the CPU. A good OS CPU dispatcher may be able to exploit all SMP CPU speed tradeoffs. Some architectures flush various lavels of cache, registers, instruction buffers and VM translation as you change threads or especially if you change processes for both accuracy and security, but others benefit by keeping one active job as the only one on one CPU, where some or all that stuff is already loaded with good data more local than RAM.

Last edited by DGPickett; 10-15-2010 at 11:05 AM..
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PIIXPCIB(4)						   BSD Kernel Interfaces Manual 					       PIIXPCIB(4)

NAME
piixpcib -- Intel PIIX4 PCI-ISA bridge with SpeedStep SYNOPSIS
piixpcib* at pci? dev ? function ? isa* at piixpcib? DESCRIPTION
The piixpcib driver provides support for the Intel PIIX and compatible PCI-ISA Bridges with Intel's first generation SpeedStep. Frequency scaling is supported on Pentium III with two voltage modes, used by SpeedStep as power states low and high. The driver will switch into low power state by reducing voltage and frequency of the CPU. The factor depends on the processor itself, but will always reduce power consumption about 1/2. The user can manually control the CPU frequency with the sysctl(8) program using the following node: machdep.speedstep_state = [0/1] SEE ALSO
est(4), isa(4), pci(4), apmd(8), sysctl(8) HISTORY
The piixpcib driver first appeared in FreeBSD 5.5 and then in NetBSD 4.0. AUTHORS
The current piixpcib driver was written by Bruno Ducrot. It was ported to NetBSD by Jared D. McNeill <jmcneill@NetBSD.org>. BSD
March 1, 2011 BSD
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