vme_univ_manual_setup(7)				 Miscellaneous Information Manual				  vme_univ_manual_setup(7)

NAME

       vme_univ_manual_setup,  sys_attrs_vba_univ  -  Describes how to set up UNIVERSE II-based Alpha VME systems for use on the VMEbus, including
       how to modify attributes of the vba_univ kernel subsystem

DESCRIPTION

       VMEbus UNIVERSE II setup allows you to run the operating system on UNIVERSE II-based Alpha VME systems.	For information  about	installing
       the operating system on these systems, see the Installation Guide.

       For information about setting up VIP/VIC-based Alpha VME systems for use on the VMEbus, see the sys_attrs_vba_vipvic(7) reference page.

       See System Configuration Supplement: OEM Platforms for detailed information about the use of the VMEbus on UNIVERSE II-based Alpha VME sys-
       tems, including the following topics: Configuring the vba_univ subsystem  Configuring  PCI-to-VME  address  spaces  Configuring	a  special
       A24/A16 PCI-to-VME window Configuring VME-to-PCI address spaces Mapping UNIVERSE II CSRs to the VMEbus Mapping a location monitor window to
       the VMEbus Configuring VMEbus interrupts Using VMEbus software byte swapping Sharing memory between big endian and little endian processors
       Performing  VMEbus slave block transfers Performing VMEbus master block transfers with local DMA Using the realtime interrupt-handling rou-
       tine rt_post_callout

       The defaults supplied for various VMEbus parameters are listed below.  The default values specified should provide proper VMEbus  operation
       for  most  applications.   Be  careful  when modifying these values;  not all adapters support all fields.  Parameter		   Default
       Meaning -------------------------------------------------------------------- VBA_ISR_Dispatch_Policy 1		 Adapter  interruupt  dis-
       patch
					   policy is to process all
					   interrupts for the current SPL
					   level (only)

       VBA_Max_PCI_Sg_Size     0x20000000  Maximum PCI scatter/gather size
					   is 512 MB

       VBA_Max_DMA_Wndw_Size   0x4000000   Maximum DMA window size is 64 MB

       PCI_Coupled_Wndw_Tmr    0x2	   Coupled Window Timer set to hold
					   VMEbus for 32 PCI clock cycles
					   after a coupled transaction

       PCI_Max_Retry	       0xF	   PCI maximum retries before
					   signaling error set to 960
					   (value*64)

       PCI_Posted_Wrt_On_Cnt   0x0	   PCI posted write transfer count
					   is 128 bytes

       PCI_Aligned_Burst_Size  0x1	   PCI aligned burst size is 64
					   bytes

       VME_Br_Lev	       0x3	   Bus request level 3 for master
					   cycles

       VME_Fair_Req	       0x1	   VMEbus request mode is fair (not
					   demand)

       VME_Rel_Mode	       0x1	   Release mode is release on
					   request (ROR)

       VME_Bus_To	       0x6	   VMEbus timeout period is 512
					   microseconds

       VME_Arb_Mode	       0x0	   Arbitration mode is round robin

       VME_Arb_To	       0x1	   VMEbus arbitration timeout
					   period is 16 microseconds

       VME_Syscon	       0x1	   System controller VMEbus reset
					   is enabled

       VME_Von_D64	       0x4	   VMEbus On counter for D64 MBLT:
					   hold bus tenure for 2048 bytes

       VME_Voff_D64	       0x9	   VMEbus Off counter for D64 MBLT:
					   DMA interleave is 4 microseconds

       VME_Von_D32	       0x2	   VMEbus On counter for D32 MBLT:
					   hold bus tenure for 512 bytes

       VME_Voff_D32	       0x9	   VMEbus Off counter for D32 MBLT:
					   DMA	interleave  is 4 microseconds --------------------------------------------------------------------
       For   the   special   A24/A16   PCI-to-VME   (PCI   slave)   window:   --------------------------------------------------------------------
       VME_A24_A16_Wnd_Ena     1	   Special A24/A16 PCI-to-VME
					   window (64 MB) is enabled

       VME_A24_A16_Wnd_WP_Ena  1	   Write posting enabled to the
					   A24/A16 window

       VME_A24_A16_Wnd_Dwdth   0xF	   A24/A16 window maximum data
					   width is D32 (all quadrants)

       PCI_SLSI_Base	       0	   Stores A24/A16 (64 MB) window
					   base address (obtained from
					   firmware)

       VME_A24_Size	       0xFF0000    Stores the size of each A24
					   address space within the A24/A16
					   window; obtainable via sysconfig
					   -q, default is 16MB-64KB

       VME_A16_Size	       0x10000	   Stores the size of each A16
					   address space within the A24/A16
					   window; obtainable via sysconfig
					   -q, default is 64KB -------------------------------------------------------------------- For PCI-to-VME
       (PCI  slave)  windows  0  through   7:	--------------------------------------------------------------------   PCI_LSI_Base		 0
       Stores base address of the
					   contiguous PCI dense space
					   available for PCI-to-VME windows
					   (obtained from firmware)

       PCI_Mem_Avail	       0	   Stores number of bytes allocated by
					   firmware for PCI-to-VME windows

       PCI_Mem_Free	       0	   Stores number of bytes available
					   for further PCI-to-VME window
					   allocations

       VME_Wnd0_Ena		1	     Window  0	is  enabled:  VME_Wnd0_VME_Address     0x80000000     VMEbus  base  address  is 0x80000000
       VME_Wnd0_Size		0x08000000     Size  is  128  MB  VME_Wnd0_AM_Space	   2		  A32  space   VME_Wnd0_AM_Usr_Sprvsr	 1
       User mode VME_Wnd0_AM_Data_Prg	 1	       Data access VME_Wnd0_Dwdth	   2		 Maximum data width is D32 VME_Wnd0_WP_Ena
       1	     Write posting enabled VME_Wnd0_Cycle_Sel	   0		 VMEbus single cycles only

       VME_Wnd1_Ena	       1	    Window  1  is  enabled:  VME_Wnd1_VME_Address     0x80000000     VMEbus  base  address  is	0x80000000
       VME_Wnd1_Size		 0x08000000	 Size  is  128	MB  VME_Wnd1_AM_Space	     2		    A32  space	VME_Wnd1_AM_Usr_Sprvsr	 1
       User  mode  VME_Wnd1_AM_Data_Prg     2		   Program  access  VME_Wnd1_Dwdth	     2		    Maximum  data  width  is   D32
       VME_Wnd1_WP_Ena	       1	     Write posting enabled VME_Wnd1_Cycle_Sel	   0		 VMEbus single cycles only

       VME_Wnd2_Ena		1	     Window  2	is  enabled:  VME_Wnd2_VME_Address     0x80000000     VMEbus  base  address  is 0x80000000
       VME_Wnd2_Size		0x08000000     Size  is  128  MB  VME_Wnd2_AM_Space	   2		  A32  space   VME_Wnd2_AM_Usr_Sprvsr	 2
       Supervisory  mode  VME_Wnd2_AM_Data_Prg	   1		  Data	access	VME_Wnd2_Dwdth		 2		Maximum  data width is D32
       VME_Wnd2_WP_Ena	       1	     Write posting enabled VME_Wnd2_Cycle_Sel	   0		 VMEbus single cycles only

       VME_Wnd3_Ena	       1	    Window  3  is  enabled:  VME_Wnd3_VME_Address     0x80000000     VMEbus  base  address  is	0x80000000
       VME_Wnd3_Size		 0x08000000	 Size  is  128	MB  VME_Wnd3_AM_Space	     2		    A32  space	VME_Wnd3_AM_Usr_Sprvsr	 2
       Supervisory mode VME_Wnd3_AM_Data_Prg	2	      Program access VME_Wnd3_Dwdth	      2 	     Maximum  data  width  is  D32
       VME_Wnd3_WP_Ena	       1	     Write posting enabled VME_Wnd3_Cycle_Sel	   0		 VMEbus single cycles only

       VME_Wnd4_Ena		 1	      Window  4  is  enabled:  VME_Wnd4_VME_Address	0x00FF0000     VMEbus  base  address  is  0xFF0000
       VME_Wnd4_Size		0x00010000     Size  is  64  KB  VME_Wnd4_AM_Space	  1		 A24   space   VME_Wnd4_AM_Usr_Sprvsr	 1
       User mode VME_Wnd4_AM_Data_Prg	 1	       Data access VME_Wnd4_Dwdth	   2		 Maximum data width is D32 VME_Wnd4_WP_Ena
       1	     Write posting enabled VME_Wnd4_Cycle_Sel	   0		 VMEbus single cycles only

       VME_Wnd5_Ena		1	     Window  5	is  enabled:  VME_Wnd5_VME_Address     0x00FF0000     VMEbus  base  address  is   0xFF0000
       VME_Wnd5_Size		 0x00010000	 Size	is  64	KB  VME_Wnd5_AM_Space	     1		    A24  space	VME_Wnd5_AM_Usr_Sprvsr	 2
       Supervisory mode VME_Wnd5_AM_Data_Prg	1	       Data  access  VME_Wnd5_Dwdth	      2 	     Maximum  data  width  is  D32
       VME_Wnd5_WP_Ena	       1	     Write posting enabled VME_Wnd5_Cycle_Sel	   0		 VMEbus single cycles only

       VME_Wnd6_Ena		 0	       Window	6   is	 disabled  by  default	VME_Wnd6_VME_Address	 0x0  VME_Wnd6_Size	       0x0
       VME_Wnd6_AM_Space       0	     A16 space VME_Wnd6_AM_Usr_Sprvsr  1	     User mode VME_Wnd6_AM_Data_Prg    1	      Data
       access  VME_Wnd6_Dwdth		2	       Maximum	data  width  is  D32  VME_Wnd6_WP_Ena	       1	     Write posting enabled
       VME_Wnd6_Cycle_Sel      0	     VMEbus single cycles only

       VME_Wnd7_Ena		0	     Window  7	is  disabled  by   default   VME_Wnd7_VME_Address      0x0   VME_Wnd7_Size	       0x0
       VME_Wnd7_AM_Space	0	      A16 space VME_Wnd7_AM_Usr_Sprvsr	1	      User mode VME_Wnd7_AM_Data_Prg	1	      Data
       access VME_Wnd7_Dwdth	      2 	    Maximum  data  width  is  D32  VME_Wnd7_WP_Ena	    1		   Write  posting  enabled
       VME_Wnd7_Cycle_Sel	0	       VMEbus  single cycles only -------------------------------------------------------------------- For
       VME-to-PCI  (VMEbus  slave)  windows  0	through   7:   --------------------------------------------------------------------   PCI_Wnd0_Ena
       1	    Window  0 is enabled: PCI_Wnd0_VME_Address	  0x00C00000	VMEbus base address is 0xC00000 PCI_Wnd0_Size		0x00400000
       Size is 4 MB PCI_Wnd0_AM_Space	     1		    A24  space	PCI_Wnd0_AM_Usr_Sprvsr	 3		Both  user  and  supervisory  mode
       PCI_Wnd0_AM_Data_Prg	 3		 Both  data  and  program  access  PCI_Wnd0_WP_Ena	    1		   Write  posting  enabled
       PCI_Wnd0_Pre_Rd_Ena	1	       Prefetch  reads	enabled   PCI_Wnd0_PCI64_Ena	    1		    PCI64   transactions   enabled
       PCI_Wnd0_PCI_Lock_Ena   0	     Lock disabled (not modifiable)

       PCI_Wnd1_Ena		1	     Window  1	is  enabled:  PCI_Wnd1_VME_Address     0x08000000     VMEbus  base  address  is  0x8000000
       PCI_Wnd1_Size		0x08000000     Size  is  128  MB  PCI_Wnd1_AM_Space	   2		  A32  space   PCI_Wnd1_AM_Usr_Sprvsr	 3
       Both   user   and   supervisory	mode  PCI_Wnd1_AM_Data_Prg     3	      Both  data  and  program	access	PCI_Wnd1_WP_Ena 	 1
       Write posting enabled PCI_Wnd1_Pre_Rd_Ena     1		   Prefetch reads enabled PCI_Wnd1_PCI64_Ena	  1		PCI64 transactions
       enabled PCI_Wnd1_PCI_Lock_Ena   0	     Lock disabled (not modifiable)

       PCI_Wnd2_Ena		 0	       Window	2   is	 disabled  by  default	PCI_Wnd2_VME_Address	 0x0  PCI_Wnd2_Size	       0x0
       PCI_Wnd2_AM_Space       1	     A24 space PCI_Wnd2_AM_Usr_Sprvsr  3	     Both user and supervisory	mode  PCI_Wnd2_AM_Data_Prg
       3	      Both  data  and  program	access	PCI_Wnd2_WP_Ena 	 1		Write  posting	enabled  PCI_Wnd2_Pre_Rd_Ena	 1
       Prefetch reads enabled PCI_Wnd2_PCI64_Ena      1 	    PCI64 transactions enabled PCI_Wnd2_PCI_Lock_Ena   0	     Lock disabled
       (not modifiable)

       PCI_Wnd3_Ena		 0	       Window	3   is	 disabled  by  default	PCI_Wnd3_VME_Address	 0x0  PCI_Wnd3_Size	       0x0
       PCI_Wnd3_AM_Space       1	     A24 space PCI_Wnd3_AM_Usr_Sprvsr  3	     Both user and supervisory	mode  PCI_Wnd3_AM_Data_Prg
       3	      Both  data  and  program	access	PCI_Wnd3_WP_Ena 	 1		Write  posting	enabled  PCI_Wnd3_Pre_Rd_Ena	 1
       Prefetch reads enabled PCI_Wnd3_PCI64_Ena      1 	    PCI64 transactions enabled PCI_Wnd3_PCI_Lock_Ena   0	     Lock disabled
       (not modifiable)

       PCI_Wnd4_Ena		 0	       Window	4   is	 disabled  by  default	PCI_Wnd4_VME_Address	 0x0  PCI_Wnd4_Size	       0x0
       PCI_Wnd4_AM_Space       1	     A24 space PCI_Wnd4_AM_Usr_Sprvsr  3	     Both user and supervisory	mode  PCI_Wnd4_AM_Data_Prg
       3	      Both  data  and  program	access	PCI_Wnd4_WP_Ena 	 1		Write  posting	enabled  PCI_Wnd4_Pre_Rd_Ena	 1
       Prefetch reads enabled PCI_Wnd4_PCI64_Ena      1 	    PCI64 transactions enabled PCI_Wnd4_PCI_Lock_Ena   0	     Lock disabled
       (not modifiable)

       PCI_Wnd5_Ena		 0	       Window	5   is	 disabled  by  default	PCI_Wnd5_VME_Address	 0x0  PCI_Wnd5_Size	       0x0
       PCI_Wnd5_AM_Space       1	     A24 space PCI_Wnd5_AM_Usr_Sprvsr  3	     Both user and supervisory	mode  PCI_Wnd5_AM_Data_Prg
       3	      Both  data  and  program	access	PCI_Wnd5_WP_Ena 	 1		Write  posting	enabled  PCI_Wnd5_Pre_Rd_Ena	 1
       Prefetch reads enabled PCI_Wnd5_PCI64_Ena      1 	    PCI64 transactions enabled PCI_Wnd5_PCI_Lock_Ena   0	     Lock disabled
       (not modifiable)

       PCI_Wnd6_Ena		 0	       Window	6   is	 disabled  by  default	PCI_Wnd6_VME_Address	 0x0  PCI_Wnd6_Size	       0x0
       PCI_Wnd6_AM_Space       1	     A24 space PCI_Wnd6_AM_Usr_Sprvsr  3	     Both user and supervisory	mode  PCI_Wnd6_AM_Data_Prg
       3	      Both  data  and  program	access	PCI_Wnd6_WP_Ena 	 1		Write  posting	enabled  PCI_Wnd6_Pre_Rd_Ena	 1
       Prefetch reads enabled PCI_Wnd6_PCI64_Ena      1 	    PCI64 transactions enabled PCI_Wnd6_PCI_Lock_Ena   0	     Lock disabled
       (not modifiable)

       PCI_Wnd7_Ena		 0	       Window	7   is	 disabled  by  default	PCI_Wnd7_VME_Address	 0x0  PCI_Wnd7_Size	       0x0
       PCI_Wnd7_AM_Space       1	     A24 space PCI_Wnd7_AM_Usr_Sprvsr  3	     Both user and supervisory	mode  PCI_Wnd7_AM_Data_Prg
       3	      Both  data  and  program	access	PCI_Wnd7_WP_Ena 	 1		Write  posting	enabled  PCI_Wnd7_Pre_Rd_Ena	 1
       Prefetch reads enabled PCI_Wnd7_PCI64_Ena      1 	    PCI64 transactions enabled PCI_Wnd7_PCI_Lock_Ena   0	     Lock disabled
       (not  modifiable) -------------------------------------------------------------------- For UNIVERSE II CSR and location monitor window map-
       ping: -------------------------------------------------------------------- CSR_Ena		   1		UNIVERSE  II  CSR  mapping
       enabled:  CSR_VME_Address	  0xFFFF0000	 VMEbus  base  address	is  0xFFFF0000	CSR_AM_Space		 2		A32  space
       CSR_AM_Usr_Sprvsr       2	     Supervisory mode CSR_AM_Data_Prg	      3 	    Both program and data access

       LM_Ena		       0	   Location monitor mapping is	LM_VME_Address		 0xFFFF1000	disabled  by  default  LM_AM_Space
       2	      A32 space LM_AM_Usr_Sprvsr	2	      Supervisory mode LM_AM_Data_Prg	       3	     Both program and data
       access

       The following VMEbus interrupt parameters provide initial defaults that are later overwritten by system priority level  (SPL)  values  sup-
       plied  by the platform.	See the values listed in System Configuration Supplement: OEM Platforms, or query the values at run time using the
       command sysconfig -q vba_univ.  Parameter	Default      Meaning  --------------------------------------------------------------------
       Irq0_SPL 	 4	     VMEbus  IRQ  level  to  system  SPL  map  Irq1_SPL 	4	   VMEbus IRQ 1 to SPL SPLDEVHIGH Irq2_SPL
       4	  VMEbus IRQ 2 to SPL SPLDEVHIGH Irq3_SPL	  4	     VMEbus IRQ 3 to SPL SPLDEVHIGH Irq4_SPL	     4		VMEbus IRQ
       4  to  SPL SPLDEVHIGH Irq5_SPL	      4 	 VMEbus IRQ 5 to SPL SPLDEVHIGH Irq6_SPL	 4	    VMEbus IRQ 6 to SPL SPLDEVHIGH
       Irq7_SPL 	4	   VMEbus IRQ 7 to SPL SPLDEVHIGH Adapt_Blk_SPL    4	      Adapter resource blocking SPL
				   SPLDEVHIGH

RELATED INFORMATION

       Interfaces:  sys_attrs_vme_vba(7), sys_attrs_vba_vipvic(7), sysconfigdb(8), sys_attrs(5)

       System Configuration Supplement: OEM Platforms, Device Driver Kit manual Writing VMEbus Device Drivers delim off

															  vme_univ_manual_setup(7)