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Special Forums News, Links, Events and Announcements Software Releases - RSS News DOLPHIN SMASH 5.10.0 (Default branch)
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Old 01-31-2008
DOLPHIN SMASH 5.10.0 (Default branch)
ImageDolphin Smash is a mixed-signal, multi-language simulator for IC or PCB designs. It uses SPICE syntax for analog descriptions, Verilog-HDL and VHDL for digital, Verilog-A/AMS, VHDL-AMS and ABCD (a combination of SPICE and C) for analog behavioral, and C for DSP algorithms.License: Free To Use But RestrictedChanges:
Numerous enhancements including hierarchical analog power computing, computing and tracing of analog net resistive and capacitive impedance, and PSP (Penn State and Philips) and EKV3 MOSFET models.Image

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verilog::netlist::modport

Netlist::ModPort(3pm)					User Contributed Perl Documentation				     Netlist::ModPort(3pm)

NAME

       Verilog::Netlist::ModPort - ModPort within a Verilog Interface

SYNOPSIS

	 use Verilog::Netlist;

	 ...
	 my $interface = $netlist->find_interface('name');
	 my $modport =	$interface->find_modport('name')

DESCRIPTION

       A Verilog::Netlist::ModPort object is created by Verilog::Netlist::Interface for every modport under the interface.

METHODS

       See also Verilog::Netlist::Subclass for additional accessors and methods.

       $self->comment
	   Returns any comments following the definition.  keep_comments=>1 must be passed to Verilog::Netlist::new for comments to be retained.

       $self->dump
	   Prints debugging information for this modport.

       $self->find_port(name)
	   Returns Verilog::Netlist::Net matching given name.

       $self->find_port_by_index
	   Returns the port name associated with the given index.

       $self->module
	   Returns Verilog::Netlist::Interface the ModPort belongs to.

       $self->lint
	   Checks the modport for errors.

       $self->name
	   The name of the modport.

       $self->netlist
	   Reference to the Verilog::Netlist the modport is under.

       $self->nets
	   Returns list of references to Verilog::Netlist::Net in the interface.

       $self->nets_sorted
	   Returns list of name sorted references to Verilog::Netlist::Net in the interface.

       $self->nets_and_ports_sorted
	   Returns list of name sorted references to Verilog::Netlist::Net and Verilog::Netlist::Port in the modport.

       $self->ports
	   Returns list of references to Verilog::Netlist::Port in the modport.

       $self->ports_ordered
	   Returns list of references to Verilog::Netlist::Port in the modport sorted by pin number.

       $self->ports_sorted
	   Returns list of references to Verilog::Netlist::Port in the modport sorted by name.

       $self->verilog_text
	   Returns verilog code which represents this modport.	Returned as an array that must be joined together to form the final text string.
	   The netlist must be already ->link'ed for this to work correctly.

DISTRIBUTION

       Verilog-Perl is part of the <http://www.veripool.org/> free Verilog EDA software tool suite.  The latest version is available from CPAN and
       from http://www.veripool.org/verilog-perl <http://www.veripool.org/verilog-perl>.

       Copyright 2000-2012 by Wilson Snyder.  This package is free software; you can redistribute it and/or modify it under the terms of either
       the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0.

AUTHORS

       Wilson Snyder <wsnyder@wsnyder.org>

SEE ALSO

       Verilog-Perl, Verilog::Netlist::Subclass Verilog::Netlist::Interface Verilog::Netlist

perl v5.14.2							    2012-05-04						     Netlist::ModPort(3pm)