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DOLPHIN SMASH 5.10.0 (Default branch)
01-31-2008
Dolphin Smash is a mixed-signal, multi-language simulator for IC or PCB designs. It uses SPICE syntax for analog descriptions, Verilog-HDL and VHDL for digital, Verilog-A/AMS, VHDL-AMS and ABCD (a combination of SPICE and C) for analog behavioral, and C for DSP algorithms.License: Free To Use But RestrictedChanges:|
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Netlist::Defparam(3pm) User Contributed Perl Documentation Netlist::Defparam(3pm) NAME
Verilog::Netlist::Defparam - Defparam assignment SYNOPSIS
use Verilog::Netlist; ... foreach my $cont ($module->statements) print $cont->name; DESCRIPTION
A Verilog::Netlist::Defparam object is created by Verilog::Netlist for every defparam in the current module. ACCESSORS
See also Verilog::Netlist::Subclass for additional accessors and methods. $self->keyword Keyword used to declare the assignment. Currently "defparam" is the only supported value. $self->lhs Left hand side of the assignment. $self->module Pointer to the module the cell is in. $self->netlist Reference to the Verilog::Netlist the cell is under. $self->rhs Right hand side of the assignment. MEMBER FUNCTIONS
See also Verilog::Netlist::Subclass for additional accessors and methods. $self->dump Prints debugging information for this cell. DISTRIBUTION
Verilog-Perl is part of the <http://www.veripool.org/> free Verilog EDA software tool suite. The latest version is available from CPAN and from http://www.veripool.org/verilog-perl <http://www.veripool.org/verilog-perl>. Copyright 2000-2012 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. AUTHORS
Wilson Snyder <wsnyder@wsnyder.org> SEE ALSO
Verilog-Perl, Verilog::Netlist::Subclass Verilog::Netlist perl v5.14.2 2012-05-04 Netlist::Defparam(3pm)