05-28-2014
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Vim function to generate RTL Code(finite state machine) in verilog
Hi I wanted to call the AutoFsm function (given below) in vim to generate a code something like:
**********verilog code to generate *************
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
state_r <= #1 next_stateascii_r;
end else begin
state_r <= #1 next_stateascii_r;
end
end
always @(state_r) begin
next_stateascii_r = state_r
casex ({state_r})
SM_IDLE: next_stateascii_r = "idle ";
SM_SEND: next_stateascii_r = "send ";
SM_WAIT1: next_stateascii_r = "wait1";
default: next_stateascii_r = "%Erro";
endcase
end
**********end of verilog code to generate *************
function AutoFsm() "{{{2
let aft_fsm = []
call KillAutoFsm()
for line in getline(1, line("$"))
if line =~ '/\*\<autofsm\>'
call add(aft_fsm, line)
call add(aft_fsm, "// Define fsm here")
let line = substitute(line,'^.*\<autofsm\>\s*','','')
let line = substitute(line,'\s*\*/.*$','','')
let paras = split(line,'\s\+')
let state = paras[0]
let inst_state = paras[1]
let autoparaline = s:GetSpecAutoParaLine(state)
let paras = s:GetAutoParas(autoparaline)
let first_st = ''
for key in keys(paras[0])
let first_st = key
endfor
call add(aft_fsm, "always @(posedge clk or negedge rst_n) begin")
call add(aft_fsm, s:indent . "if(!rst_n) begin")
call add(aft_fsm, s:indent . s:indent . inst_state . ' <= #1 ' . first_st . ';')
call add(aft_fsm, s:indent . "end else begin")
call add(aft_fsm, s:indent . s:indent . inst_state . ' <= #1 ' . 'next_' . inst_state . ';')
call add(aft_fsm, s:indent . "end")
call add(aft_fsm, "end")
call add(aft_fsm, "always @(*) begin")
call add(aft_fsm, s:indent . 'next_' . inst_state . ' = ' . inst_state . ';')
call add(aft_fsm, s:indent . 'case(' . inst_state . ')')
for para in paras
for key in keys(para)
call add(aft_fsm, s:indent . s:indent . key . ': begin')
call add(aft_fsm, s:indent . s:indent . 'end')
endfor
endfor
call add(aft_fsm, s:indent . s:indent . 'default' . ': begin')
call add(aft_fsm, s:indent . s:indent . 'end')
call add(aft_fsm, s:indent . 'endcase')
call add(aft_fsm, "end")
call add(aft_fsm, "// End of automatic fsm")
elseif line =~ '^\s*\<endmodule\>'
call add(aft_fsm, line)
break
else
call add(aft_fsm, line)
endif
endfor
call s:UpdateBuf(aft_fsm,-1)
endfunction "}}}2
Please let me know the arguments & their format which i need to give so as to generate the verilog code using AutoFsm function.
Last edited by dll_fpga; 05-28-2014 at 05:30 PM..