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PMC.XSCALE(3) BSD Library Functions Manual PMC.XSCALE(3)
NAME
pmc.xscale -- measurement events for Intel XScale family CPUs
LIBRARY
Performance Counters Library (libpmc, -lpmc)
SYNOPSIS
#include <pmc.h>
DESCRIPTION
Intel XScale CPUs are ARM CPUs based on the ARMv5e core.
Second generation cores have 2 counters, while third generation cores have 4 counters. Third generation cores also have an increased number
of PMC events.
Intel XScale PMCs are documented in 3rd Generation Intel XScale Microarchitecture Developer's Manual, May 2007.
Event Specifiers (Programmable PMCs)
Intel XScale programmable PMCs support the following events:
IC_FETCH
External memory fetch due to L1 instruction cache miss.
IC_MISS
Instruction cache or TLB miss.
DATA_DEPENDENCY_STALLED
A data dependency stalled
ITLB_MISS
Instruction TLB miss.
DTLB_MISS
Data TLB miss.
BRANCH_RETIRED
Branch instruction retired (executed).
BRANCH_MISPRED
Branch mispredicted.
INSTR_RETIRED
Instructions retired (executed).
DC_FULL_CYCLE
L1 data cache buffer full stall. Event occurs on every cycle the condition is present.
DC_FULL_CONTIG
L1 data cache buffer full stall. Event occurs once for each contiguous sequence of this type of stall.
DC_ACCESS
L1 data cache access, not including cache operations.
DC_MISS
L1 data cache miss, not including cache operations.
DC_WRITEBACK
L1 data cache write-back. Occurs for each cache line that's written back from the cache.
PC_CHANGE
Software changed the program counter.
BRANCH_RETIRED_ALL
Branch instruction retired (executed). This event counts all branch instructions, indirect or direct.
INSTR_CYCLE
Count the number of microarchitecture cycles each instruction requires to issue.
CP_STALL
Coprocessor stalled the instruction pipeline.
PC_CHANGE_ALL
Software changed the program counter (includes exceptions).
PIPELINE_FLUSH
Pipeline flushes due to mispredictions or exceptions.
BACKEND_STALL
Backend stalled the instruction pipeline.
MULTIPLIER_USE
Multiplier used.
MULTIPLIER_STALLED
Multiplier stalled the instruction pipeline.
DATA_CACHE_STALLED
Data cache stalled the instruction pipeline.
L2_CACHE_REQ
L2 cache request, not including cache operations.
L2_CACHE_MISS
L2 cache miss, not including cache operations.
ADDRESS_BUS_TRANS
Address bus transaction.
SELF_ADDRESS_BUS_TRANS
Self initiated address bus transaction.
DATA_BUS_TRANS
Data bus transaction.
Event Name Aliases
The following table shows the mapping between the PMC-independent aliases supported by Performance Counters Library (libpmc, -lpmc) and the
underlying hardware events used.
Alias Event
branches BRANCH_RETIRED
branch-mispredicts BRANCH_MISPRED
dc-misses DC_MISS
ic-misses IC_MISS
instructions INSTR_RETIRED
SEE ALSO
pmc(3), pmc.soft(3), pmc_cpuinfo(3), pmclog(3), hwpmc(4)
HISTORY
The pmc library first appeared in FreeBSD 6.0. Intel XScale support first appeared in FreeBSD 9.0.
AUTHORS
The Performance Counters Library (libpmc, -lpmc) library was written by Joseph Koshy <jkoshy@FreeBSD.org>.
Intel XScale support was added by Rui Paulo <rpaulo@FreeBSD.org>.
CAVEATS
The Intel XScale code does not yet support sampling.
BSD
December 23, 2009 BSD
What is Performance data nad Event data?