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Plan 9 - man page for getfcr (plan9 section 2)

GETFCR(2)			       System Calls Manual				GETFCR(2)

       getfcr, setfcr, getfsr, setfsr - control floating point

       #include <u.h>
       #include <libc.h>

       ulong getfcr(void)

       void setfcr(ulong fcr)

       ulong getfsr(void)

       void setfsr(ulong fsr)

       /* Alef only */

       #include <arch.h>
       #include <alef.h>

       uint getfcr()

       void setfcr(uint fcr)

       uint getfsr()

       void setfsr(uint fsr)

       These  routines	provide a fairly portable interface to control the rounding and exception
       characteristics of IEEE 754 floating point units.   In  effect,	they  define  a  pair  of
       pseudo-registers, the floating point control register, fcr, which affects rounding, preci-
       sion, and exceptions, and the floating point status register, fsr, which holds the accrued
       exception  bits.   Each register has a get routine to retrieve its value, a set routine to
       modify it, and macros that identify its contents.

       The fcr contains bits that, when set, enable exceptions:  FPINEX  (enable  inexact  excep-
       tions),	FPOVFL	(enable  overflow  exceptions), FPUNFL (enable underflow exceptions), and
       FPZDIV (enable zero divide exceptions).	Rounding is  controlled  by  installing  in  fcr,
       under mask FPRMASK, one of the values FPRNR (round to nearest), FPRZ (round towards zero),
       FPRPINF (round towards positive infinity), and FPRNINF (round towards negative  infinity).
       Precision is controlled by installing in fcr, under mask FPPMASK, one of the values FPPEXT
       (extended precision), FPPSGL (single precision), and FPPDBL (double precision).

       The fsr holds the accrued exception bits FPAINEX, FPAOVFL, FPAUNFL,  and  FPAZDIV,  corre-
       sponding to the fsr bits without the A in the name.

       Not  all  machines support all modes.  If the corresponding mask is zero, the machine does
       not support the rounding or precision modes.  On some machines it is not possible to clear
       selective  accrued  exception  bits; a setfsr clears them all.  The exception bits defined
       here work on all architectures.

       The default state of the floating point unit is fixed for  a  given  architecture  but  is
       undefined  across  Plan	9:  the  default  is to provide what the hardware does most effi-
       ciently.  Use these routines if you need guaranteed behavior.  Also, gradual underflow  is
       not available on some machines.

       The specification for these routines is the same in Alef, except that these functions (and
       only   these   functions)    need    the    machine-dependent	include    file    /$obj-

       To  enable  overflow  traps  and  make sure registers are rounded to double precision (for
       example on the MC68020, where the internal registers are 80 bits long):

	      ulong fcr;
	      fcr = getfcr();
	      fcr |= FPOVFL;
	      fcr &= ~FPPMASK;
	      fcr |= FPPDBL;



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