getfcr(2) [plan9 man page]
GETFCR(2) System Calls Manual GETFCR(2) NAME
getfcr, setfcr, getfsr, setfsr - control floating point SYNOPSIS
#include <u.h> #include <libc.h> ulong getfcr(void) void setfcr(ulong fcr) ulong getfsr(void) void setfsr(ulong fsr) /* Alef only */ #include <arch.h> #include <alef.h> uint getfcr() void setfcr(uint fcr) uint getfsr() void setfsr(uint fsr) DESCRIPTION
These routines provide a fairly portable interface to control the rounding and exception characteristics of IEEE 754 floating point units. In effect, they define a pair of pseudo-registers, the floating point control register, fcr, which affects rounding, precision, and excep- tions, and the floating point status register, fsr, which holds the accrued exception bits. Each register has a get routine to retrieve its value, a set routine to modify it, and macros that identify its contents. The fcr contains bits that, when set, enable exceptions: FPINEX (enable inexact exceptions), FPOVFL (enable overflow exceptions), FPUNFL (enable underflow exceptions), and FPZDIV (enable zero divide exceptions). Rounding is controlled by installing in fcr, under mask FPRMASK, one of the values FPRNR (round to nearest), FPRZ (round towards zero), FPRPINF (round towards positive infinity), and FPRNINF (round towards negative infinity). Precision is controlled by installing in fcr, under mask FPPMASK, one of the values FPPEXT (extended precision), FPPSGL (single precision), and FPPDBL (double precision). The fsr holds the accrued exception bits FPAINEX, FPAOVFL, FPAUNFL, and FPAZDIV, corresponding to the fsr bits without the A in the name. Not all machines support all modes. If the corresponding mask is zero, the machine does not support the rounding or precision modes. On some machines it is not possible to clear selective accrued exception bits; a setfsr clears them all. The exception bits defined here work on all architectures. The default state of the floating point unit is fixed for a given architecture but is undefined across Plan 9: the default is to provide what the hardware does most efficiently. Use these routines if you need guaranteed behavior. Also, gradual underflow is not available on some machines. Alef The specification for these routines is the same in Alef, except that these functions (and only these functions) need the machine-dependent include file /$objtype/include/alef/arch.h. EXAMPLE
To enable overflow traps and make sure registers are rounded to double precision (for example on the MC68020, where the internal registers are 80 bits long): ulong fcr; fcr = getfcr(); fcr |= FPOVFL; fcr &= ~FPPMASK; fcr |= FPPDBL; setfcr(fcr); SOURCE
/sys/src/libc/$objtype/getfcr.s GETFCR(2)
Check Out this Related Man Page
fpgetround(3C) Standard C Library Functions fpgetround(3C) NAME
fpgetround, fpsetround, fpgetmask, fpsetmask, fpgetsticky, fpsetsticky - IEEE floating-point environment control SYNOPSIS
#include <ieeefp.h> fp_rnd fpgetround(void); fp_rnd fpsetround(fp_rnd rnd_dir); fp_except fpgetmask(void); fp_except fpsetmask(fp_except mask); fp_except fpgetsticky(void); fp_except fpsetsticky(fp_except sticky); DESCRIPTION
There are five floating-point exceptions: o divide-by-zero, o overflow, o underflow, o imprecise (inexact) result, and o invalid operation. When a floating-point exception occurs, the corresponding sticky bit is set(1), and if the mask bit is enabled(1), the trap takes place. These routines let the user change the behavior on occurrence of any of these exceptions, as well as change the rounding mode for floating- point operations. The mask argument is formed by the logical OR operation of the following floating-point exception masks: FP_X_INV /* invalid operation exception */ FP_X_OFL /* overflow exception */ FP_X_UFL /* underflow exception */ FP_X_DZ /* divide-by-zero exception */ FP_X_IMP /* imprecise (loss of precision) */ The following floating-point rounding modes are passed to fpsetround and returned by fpgetround(). FP_RN /* round to nearest representative number */ FP_RP /* round to plus infinity */ FP_RM /* round to minus infinity */ FP_RZ /* round to zero (truncate) */ The default environment is rounding mode set to nearest (FP_RN) and all traps disabled. The fpsetsticky() function modifies all sticky flags. The fpsetmask() function changes all mask bits. The fpsetmask() function clears the sticky bit corresponding to any exception being enabled. RETURN VALUES
The fpgetround() function returns the current rounding mode. The fpsetround() function sets the rounding mode and returns the previous rounding mode. The fpgetmask() function returns the current exception masks. The fpsetmask() function sets the exception masks and returns the previous setting. The fpgetsticky() function returns the current exception sticky flags. The fpsetsticky() function sets (clears) the exception sticky flags and returns the previous setting. USAGE
The C programming language requires truncation (round to zero) for floating point to integral conversions. The current rounding mode has no effect on these conversions. The sticky bit must be cleared to recover from the trap and proceed. If the sticky bit is not cleared before the next trap occurs, a wrong exception type may be signaled. Individual bits may be examined using the constants defined in <ieeefp.h>. ATTRIBUTES
See attributes(5) for descriptions of the following attributes: +-----------------------------+-----------------------------+ | ATTRIBUTE TYPE | ATTRIBUTE VALUE | +-----------------------------+-----------------------------+ |MT-Level |MT-Safe | +-----------------------------+-----------------------------+ SEE ALSO
isnand(3C), attributes(5) SunOS 5.11 29 Dec 1996 fpgetround(3C)