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atomic_ops(3) [netbsd man page]

ATOMIC_OPS(3)						   BSD Library Functions Manual 					     ATOMIC_OPS(3)

atomic_ops -- atomic memory operations SYNOPSIS
#include <sys/atomic.h> DESCRIPTION
The atomic_ops family of functions provide atomic memory operations. There are 7 classes of atomic memory operations available: atomic_add(3) These functions perform atomic addition. atomic_and(3) These functions perform atomic logical ``and''. atomic_cas(3) These functions perform atomic compare-and-swap. atomic_dec(3) These functions perform atomic decrement. atomic_inc(3) These functions perform atomic increment. atomic_or(3) These functions perform atomic logical ``or''. atomic_swap(3) These functions perform atomic swap. Synchronization Mechanisms Where the architecture does not provide hardware support for atomic compare and swap (CAS), atomicity is provided by a restartable sequence or by a spinlock. The chosen method is not ordinarily distinguishable by or visible to users of the interface. The following architectures can be assumed to provide CAS in hardware: alpha, amd64, i386, powerpc, powerpc64, sparc64. Scope and Restrictions If hardware CAS is available, the atomic operations are globally atomic: operations within a memory region shared between processes are guar- anteed to be performed atomically. If hardware CAS is not available, it may only be assumed that the operations are atomic with respect to threads in the same process. Additionally, if hardware CAS is not available, the atomic operations must not be used within a signal handler. Users of atomic memory operations should not make assumptions about how the memory access is performed (specifically, the width of the memory access). For this reason, applications making use of atomic memory operations should limit their use to regular memory. The results of using atomic memory operations on anything other than regular memory are undefined. Users of atomic memory operations should take care to modify any given memory location either entirely with atomic operations or entirely with some other synchronization mechanism. Intermixing of atomic operations with other synchronization mechanisms for the same memory loca- tion results in undefined behavior. Visibility and Ordering of Memory Accesses If hardware CAS is available, stores to the target memory location by an atomic operation will reach global visibility before the operation completes. If hardware CAS is not available, the store may not reach global visibility until some time after the atomic operation has com- pleted. However, in all cases a subsequent atomic operation on the same memory cell will be delayed until the result of any preceeding oper- ation has reached global visibility. Atomic operations are strongly ordered with respect to each other. The global visibility of other loads and stores before and after an atomic operation is undefined. Applications that require synchronization of loads and stores with respect to an atomic operation must use memory barriers. See membar_ops(3). Performance Because atomic memory operations require expensive synchronization at the hardware level, applications should take care to minimize their use. In certain cases, it may be more appropriate to use a mutex, especially if more than one memory location will be modified. SEE ALSO
atomic_add(3), atomic_and(3), atomic_cas(3), atomic_dec(3), atomic_inc(3), atomic_or(3), atomic_swap(3), membar_ops(3) HISTORY
The atomic_ops functions first appeared in NetBSD 5.0. BSD
April 14, 2010 BSD

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atomic_ops(3C)															    atomic_ops(3C)

atomic_ops - atomic operations SYNOPSIS
#include <atomic.h> This collection of functions provides atomic memory operations. There are 8 different classes of atomic operations: atomic_add(3C) These functions provide an atomic addition of a signed value to a variable. atomic_and(3C) These functions provide an atomic logical 'and' of a value to a variable. atomic_bits(3C) These functions provide atomic bit setting and clearing within a variable. atomic_cas(3C) These functions provide an atomic comparison of a value with a variable. If the comparison is equal, then swap in a new value for the variable, returning the old value of the variable in either case. atomic_dec(3C) These functions provide an atomic decrement on a variable. atomic_inc(3C) These functions provide an atomic increment on a variable. atomic_or(3C) These functions provide an atomic logical 'or' of a value to a variable. atomic_swap(3C) These functions provide an atomic swap of a value with a variable, returning the old value of the variable. See attributes(5) for descriptions of the following attributes: +-----------------------------+-----------------------------+ | ATTRIBUTE TYPE | ATTRIBUTE VALUE | +-----------------------------+-----------------------------+ |Interface Stability |Stable | +-----------------------------+-----------------------------+ |MT-Level |MT-Safe | +-----------------------------+-----------------------------+ atomic_add(3C), atomic_and(3C), atomic_bits(3C), atomic_cas(3C), atomic_dec(3C), atomic_inc(3C), atomic_or(3C), atomic_swap(3C), mem- bar_ops(3C), attributes(5) Atomic instructions ensure global visibility of atomically-modified variables on completion. In a relaxed store order system, this does not guarantee that the visibility of other variables will be synchronized with the completion of the atomic instruction. If such synchro- nization is required, memory barrier instructions must be used. See membar_ops(3C). Atomic instructions can be expensive. since they require synchronization to occur at a hardware level. This means they should be used with care to ensure that forcing hardware level synchronization occurs a minimum number of times. For example, if you have several variables that need to be incremented as a group, and each needs to be done atomically, then do so with a mutex lock protecting all of them being incremented rather than using the atomic_inc(3C) operation on each of them. 12 Aug 2004 atomic_ops(3C)

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