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nand(4) [freebsd man page]

NAND(4) 						   BSD Kernel Interfaces Manual 						   NAND(4)

NAME
nand -- NAND Flash framework SYNOPSIS
device nand DESCRIPTION
The FreeBSD nand framework consists of a set of interfaces that aim to provide an extensible, object oriented environement for NAND con- trollers and NAND Flash memory chips from various hardware vendors, and to allow for uniform and flexible management of the NAND devices. It comprises of the following major components: o NAND Flash controller (NFC) interface. Defines methods which allow to send commands as well as send/receive data between the controller and a NAND chip. Back-end drivers for specific NAND controllers plug into this interface and implement low-level routines for a given NAND controller. This layer implements basic functionality of a NAND Flash controller. It allows to send command and address to chip, drive CS (chip select line), as well as read/write to the selected NAND chip. This layer is independent of NAND chip devices actually connected to the controller. o NAND chip interface. Provides basic operations like read page, program page, erase block. Currently three generic classes of drivers are available, which pro- vide support for the following chips: o large page o small page o ONFI-compliant This layer implements basic operations to be performed on a NAND chip, like read, program, erase, get status etc. Since these operations use specific commands (depending on the vendor), each chip has potentially its own implementation of the commands set. The framework is extensible so it is also possible to create a custom command set for a non standard chip support. o NANDbus. This layer is responsible for enumerating NAND chips in the system and establishing the hierarchy between chips and their supervising controllers. Its main purpose is detecting type of NAND chips connected to a given chip select (CS line). It also allows manages locking access to the NAND controller. NANDbus passes requests from an active chip to the chip controller. o NAND character / GEOM device. For each NAND chip found in a system a character and GEOM devices are created which allows to read / write directly to a device, as well as perform other specific operations (like via ioctl). There are two GEOM devices created for each NAND chip: o raw device o normal device Raw device allows to bypass ECC checking when reading/writing to it, while normal device always uses ECC algorithm to validate the read data. NAND character devices will be created for each NAND chip detected while probing the NAND controller. SEE ALSO
libnandfs(3), gnand(4), nandsim(4), nandfs(5), makefs(8), mount_nandfs(8), nandfs(8), nandsim(8), nandtool(8), newfs_nandfs(8), umount_nandfs(8) STANDARDS
Open NAND Flash Interface Working Group (ONFI). HISTORY
The nand framework support first appeared in FreeBSD 10.0. AUTHORS
The nand framework was designed and developed by Grzegorz Bernacki. This manual page was written by Rafal Jaworowski. BSD
March 8, 2012 BSD

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STRUCT 
SPI_MASTER(9) Serial Peripheral Interface (S STRUCT SPI_MASTER(9) NAME
struct_spi_master - interface to SPI master controller SYNOPSIS
struct spi_master { struct device dev; s16 bus_num; u16 num_chipselect; u16 dma_alignment; u16 mode_bits; u16 flags; #define SPI_MASTER_HALF_DUPLEX BIT(0) #define SPI_MASTER_NO_RX BIT(1) #define SPI_MASTER_NO_TX BIT(2) int (* setup) (struct spi_device *spi); int (* transfer) (struct spi_device *spi,struct spi_message *mesg); void (* cleanup) (struct spi_device *spi); }; MEMBERS
dev device interface to this driver bus_num board-specific (and often SOC-specific) identifier for a given SPI controller. num_chipselect chipselects are used to distinguish individual SPI slaves, and are numbered from zero to num_chipselects. each slave has a chipselect signal, but it's common that not every chipselect is connected to a slave. dma_alignment SPI controller constraint on DMA buffers alignment. mode_bits flags understood by this controller driver flags other constraints relevant to this driver setup updates the device mode and clocking records used by a device's SPI controller; protocol code may call this. This must fail if an unrecognized or unsupported mode is requested. It's always safe to call this unless transfers are pending on the device whose settings are being modified. transfer adds a message to the controller's transfer queue. cleanup frees controller-specific state DESCRIPTION
Each SPI master controller can communicate with one or more spi_device children. These make a small bus, sharing MOSI, MISO and SCK signals but not chip select signals. Each device may be configured to use a different clock rate, since those shared signals are ignored unless the chip is selected. The driver for an SPI controller manages access to those devices through a queue of spi_message transactions, copying data between CPU memory and an SPI slave device. For each such message it queues, it calls the message's completion function when the transaction completes. COPYRIGHT
Kernel Hackers Manual 2.6. July 2010 STRUCT SPI_MASTER(9)
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