dpgen_rf1d(3) [debian man page]

DPGEN_RF1D(3)						  Alliance - genlib User's Manual					     DPGEN_RF1D(3)

NAME

       DPGEN_RF1D, DPGEN_RF1DR0 - Register File with Decoder Macro-Generator

SYNOPSIS

       #include  <genlib.h>

       void GENLIB_MACRO (DPGEN_RF1D, char *modelname, long flags, long N);

       void GENLIB_MACRO (DPGEN_RF1DR0, char *modelname, long flags, long N);

DESCRIPTION

       Generate a register file of regNumber words of N bits with decoder named modelname. The DPGEN_RF1DR0 variant differs from the DPGEN_RF1D in
       that the register of address zero is stuck to zero. You can write into it, it will not change the value. When read, it will  always  return
       zero.

       How it works :

       o datain0 and datain1 : the two write busses. Only one is used to actually write the register word, it is selected by the sel signal.

       o sel : when set to '0' the datain0 is used to write the register word, otherwise it will be datain1.

       o adr, adw : the width (Y) of those signals is computed from regNumber : Y = log2(regNumber).

       o wen and ren : write enable and read enable, allows reading and writing when sets to '1'.

   TERMINAL NAMES
       1. ck : clock signal (input, 1 bit).

       2. sel : select the write bus (input, 1 bit).

       3. wen : write enable (input, 1 bit).

       4. ren : read enable (input, 1 bit).

       5. adr : the read address (input, Y bits).

       6. adw : the write address (input, Y bits).

       7. datain0 :  first write bus (input, N bits).

       8. datain1 :  second write bus (input, N bits).

       9. dataout : read bus (output, N bits).

       10.
	  vdd : power.

       11.
	  vss : ground.

EXAMPLE

       GENLIB_MACRO(DPGEN_RF1D, "model_rf1dx8_32"
			      , F_BEHAV|F_PLACE
			      , 32  /* Words size.	*/
			      , 8   /* Number of words. */
			      );

       GENLIB_LOINS( "model_rf1dx8_32"
		   , "instance1_rf1d_32"
		   , "ck"
		   , "sel"
		   , "wen"
		   , "ren"
		   , "adr[2:0]"
		   , "adw[2:0]"
		   , "datain0[31:0]"
		   , "datain1[31:0]"
		   , "dataout[31:0]"
		   , "vdd", "vss", NULL
		   );

SEE ALSO

       GENLIB_MACRO(3), genlib(1)

ASIM
/LIP6							   30 July 2004 						     DPGEN_RF1D(3)

GENLIB_LOSIG.3(October 1, 1997) 										   GENLIB_LOSIG.3(October 1, 1997)

NAME

       GENLIB_LOSIG - declare an internal logical signal, or a vector of internal logical signals

SYNOPSYS

       #include <genlib.h>
       void GENLIB_LOSIG(name)
       char *name;

ORIGIN

       This  software  belongs	to  the  ALLIANCE CAD SYSTEM developed by the ASIM team at LIP6 laboratory of Universite Pierre et Marie CURIE, in
       Paris, France.

       Web : http://asim.lip6.fr/recherche/alliance/
       E-mail : alliance-users@asim.lip6.fr

PARAMETERS

       name		   Name of a signal to be declared

DESCRIPTION

       LOSIG creates the internal signal, or the set of internal signals coresponding to a vector description, represented by  name.   See  BUS(3)
       and ELM(3) for more details on vectors.
       The  need  for declaring signal is mostly felt when one wants to create a consistent vector declaration, for file formats that do not allow
       partial or multiple declarations, like vhdl.  This way, a user can create a vector and access its member the way he wants, but still having
       an internal consistent form.

       Warning		   If  a signal is declared with LOSIG, but not used, the resulting file will have an internal node floating.  This is not
			   an error from a genlib point of view, so the user must be aware of it.

EXAMPLE

       #include <genlib.h>
       main()
       {
	    /* Create a figure to work on  */
	    GENLIB_DEF_LOFIG("cell");
	    /* Define interface *
	    GENLIB_LOCON(...
	    /* declare buses */
	    GENLIB_LOSIG("grum[23:0]");
	    GENLIB_LOSIG("iconection[0:7]");
	    /* Place an instance */
	    GENLIB_LOINS("no2_y" ,"no3" ,"grum[12]" ,"a9_s" ,"new_no3_s" ,"vdd" ,"vss" ,0);
	    GENLIB_LOINS("no2_y" ,"no4" ,"a12_s" ,"grum[6]" ,"no4_s" ,"vdd" ,"vss" ,0);
	    GENLIB_LOINS("a2_y" ,"a22" ,"no3_s" ,"grum[15]" ,"a22_s" ,"vdd" ,"vss" ,0);
	    /* Save all that on disk */
	    GENLIB_SAVE_LOFIG();
       }

SEE ALSO

       genlib(1), GENLIB_LOINS(3), GENLIB_LOCON(3), GENLIB_BUS(3), GENLIB_ELM(3).

BUG REPORT

       This tool is under development at the ASIM department of the LIP6 laboratory.
       We need your feedback to improve documentation and tools.

PROCEDURAL GENERATION LANGUAGE
					     ASIM/LIP6					   GENLIB_LOSIG.3(October 1, 1997)