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extcheck(1) [bsd man page]

EXTCHECK(1)						      General Commands Manual						       EXTCHECK(1)

NAME
extcheck - check hierarchical ext(5) files for global node connectivity and summarize number of fets, nodes, etc. SYNOPSIS
extcheck [ -c cthresh ] [ -p path ] [ -r rthresh ] [ -s sym=value ] [ -C ] [ -R ] [ -S symfile ] [ -T tech ] root DESCRIPTION
Extcheck will read an extracted circuit in the hierarchical ext(5) representation produced by Magic, check to ensure that all global nodes (those to which a label ending in an exclamantion point is attached) are fully connected in the layout, and then print a count of the num- ber of various items (nodes, fets, etc) encountered while flattening the circuit. The root of the tree to be processed is the file root.ext; it and all the files it references are recursively flattened. The following options are recognized: -c cthresh Set the capacitance threshold to cthresh femtofarads. Extcheck will count the number of explicit internodal capacitors greater than cthresh, the number of nodes whose capacitance is greater than cthresh, as well as the total number of nodes. (Other programs such as ext2sim(1) use this option as a threshold value below which a capacitor will not be output). The default value for cthresh is 10 femtofarads. -p path Normally, the path to search for .ext files is determined by looking for path commands in first ~cad/lib/magic/sys/.magic, then ~/.magic, then .magic in the current directory. If -p is specified, the colon-separated list of directories specified by path is used instead. Each of these directories is searched in turn for the .ext files in a design. -r rthresh Set the resistance threshold to rthresh ohms. Similar in function to -c, but for resistances. The default value for rthresh is 10 ohms. -s sym=value It's possible to use special attributes attached to transistor gates to control the length and width of transistors explicitly, rather than allowing them to be determined by the extractor. These attributes are of the form ext:w=width^ or ext:l=length^, where width or length can either be numeric, or textual. (The trailing ``^'' indicates that these are transistor gate attributes). If textual, they are treated as symbols which can be assigned a numeric value at the time ext2sim is run. The -s flag is used to assign numeric values to symbols. If a textual symbol appears in one of the above attributes, but isn't given a numeric value via -s (or -S below), then it is ignored; otherwise, the transistor's length or width is set to the numeric value defined for that sym- bol. (This option is not currently used by extcheck, but it is common to ext2sim(1) and other tools that are written using the extflat(3) library) -C Set the capacitance threshold to infinity. Because this avoids any internodal capacitance processing, all tools will run faster when this flag is given. -R Set the resistance threshold to infinity. -S symfile Each line in the file symfile is of the form sym=value, just like the argument to the -s flag above; the lines are interpreted in the same fashion. (This option is not currently used by extcheck, but it is common to ext2sim et. al.) -T tech Set the technology in the output .sim file to tech. This overrides any technology specified in the root .ext file. SEE ALSO
ext2dlys(1), ext2sim(1), ext2spice(1), magic(1), rsim(1), sim2spice(1), ext(5), sim(5) AUTHOR
Walter Scott BUGS
The -s mechanism is incomplete; it should allow quantities other than transistor lengths and widths to be specified. EXTCHECK(1)

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SIM(5)                                                          File Formats Manual                                                         SIM(5)

NAME
sim - format of .sim files read by esim, crystal, etc. DESCRIPTION
The simulation tools crystal(1) and esim(1) accept a circuit description in .sim format. There is a single .sim file for the entire cir- cuit, unlike Magic's ext(5) format in which there is a .ext file for every cell in a hierarchical design. A .sim file consists of a series of lines, each of which begins with a key letter. The key letter beginning a line determines how the remainder of the line is interpreted. The following are the list of key letters understood. | units: s tech: tech format: MIT|LBL|SU If present, this must be the first line in the .sim file. It identifies the technology of this circuit as tech and gives a scale factor for units of linear dimension as s. All linear dimensions appearing in the .sim file are multiplied by s to give centimi- crons. The format field signifies the sim variant. MIT and SU are compatible and understood by all tools. LBL is understood only by gemini(1). type g s d l w x y g=gattrs s=sattrs d=dattrs Defines a transistor of type type. Currently, type may be e or d for NMOS, or p or n for CMOS. The name of the node to which the gate, source, and drain of the transistor are connected are given by g, s, and d respectively. The length and width of the transis- tor are l and w. The next two tokens, x and y, are optional. If present, they give the location of a point inside the gate region of the transistor. The last three tokens are the attribute lists for the transistor gate, source, and drain. If no attributes are present for a particular terminal, the corresponding attribute list may be absent (i.e, there may be no g= field at all). The attribute lists gattrs, etc. are comma-separated lists of labels. The label names should not include any spaces, although some tools can accept label names with spaces if they are enclosed in double quotes. In version 6.4.5 and later the default format pro- duced by ext2sim is SU. In this format the attribute of the gate starting with S_ is the substrate node of the fet. The attributes of the gate, and source and substrate starting with A_, P_ are the area and perimeter (summed for that node only once) of the source and drain respectively. This addition to the format is backwards compatible. C n1 n2 cap Defines a capacitor between nodes n1 and n2. The value of the capacitor is cap femtofarads. NOTE: since many analysis tools com- pute transistor gate capacitance themselves from the transistor's area and perimeter, the capacitance between a node and substrate (GND!) normally does not include the capacitance from transistor gates connected to that node. If the .sim file was produced by ext2sim(1), check the technology file that was used to produce the original .ext files to see whether transistor gate capacitance is included or excluded; see ``Magic Maintainer's Manual #2: The Technology File'' for details. R node res Defines the lumped resistance of node node to be res ohms. This construct is only interpreted by a few programs. r node1 node2 res Defines an explicit resistor between nodes node1 and node2 of resistance res ohms. This construct is only interpreted by a few pro- grams. N node darea dperim parea pperim marea mperim As an alternative to computed capacitances, some tools expect the total perimeter and area of the polysilicon, diffusion, and metal in each node to be reported in the .sim file. The N construct associates diffusion area darea (in square centimicrons) and diffu- sion perimeter dperim (in centimicrons) with node node, polysilicon area parea and perimeter pperim, and metal area marea and perimeter mperim. This construct is technology dependent and obsolete. A node attr Associates attribute attr for node node. The string attr should contain no blanks. = node1 node2 Each node in a .sim file is named implicitly by having it appear in a transistor definition. All node names appearing in a .sim file are assumed to be distinct. Some tools, such as esim(1), recognize aliases for node names. The = construct allows the name node2 to be defined as an alias for the name node1. Aliases defined by means of this construct may not appear anywhere else in the .sim file. SEE ALSO
crystal(1), esim(1), ext2sim(1), sim2spice(1), ext(5) 4th Berkeley Distribution SIM(5)
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