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extcheck(1) [bsd man page]

EXTCHECK(1)						      General Commands Manual						       EXTCHECK(1)

extcheck - check hierarchical ext(5) files for global node connectivity and summarize number of fets, nodes, etc. SYNOPSIS
extcheck [ -c cthresh ] [ -p path ] [ -r rthresh ] [ -s sym=value ] [ -C ] [ -R ] [ -S symfile ] [ -T tech ] root DESCRIPTION
Extcheck will read an extracted circuit in the hierarchical ext(5) representation produced by Magic, check to ensure that all global nodes (those to which a label ending in an exclamantion point is attached) are fully connected in the layout, and then print a count of the num- ber of various items (nodes, fets, etc) encountered while flattening the circuit. The root of the tree to be processed is the file root.ext; it and all the files it references are recursively flattened. The following options are recognized: -c cthresh Set the capacitance threshold to cthresh femtofarads. Extcheck will count the number of explicit internodal capacitors greater than cthresh, the number of nodes whose capacitance is greater than cthresh, as well as the total number of nodes. (Other programs such as ext2sim(1) use this option as a threshold value below which a capacitor will not be output). The default value for cthresh is 10 femtofarads. -p path Normally, the path to search for .ext files is determined by looking for path commands in first ~cad/lib/magic/sys/.magic, then ~/.magic, then .magic in the current directory. If -p is specified, the colon-separated list of directories specified by path is used instead. Each of these directories is searched in turn for the .ext files in a design. -r rthresh Set the resistance threshold to rthresh ohms. Similar in function to -c, but for resistances. The default value for rthresh is 10 ohms. -s sym=value It's possible to use special attributes attached to transistor gates to control the length and width of transistors explicitly, rather than allowing them to be determined by the extractor. These attributes are of the form ext:w=width^ or ext:l=length^, where width or length can either be numeric, or textual. (The trailing ``^'' indicates that these are transistor gate attributes). If textual, they are treated as symbols which can be assigned a numeric value at the time ext2sim is run. The -s flag is used to assign numeric values to symbols. If a textual symbol appears in one of the above attributes, but isn't given a numeric value via -s (or -S below), then it is ignored; otherwise, the transistor's length or width is set to the numeric value defined for that sym- bol. (This option is not currently used by extcheck, but it is common to ext2sim(1) and other tools that are written using the extflat(3) library) -C Set the capacitance threshold to infinity. Because this avoids any internodal capacitance processing, all tools will run faster when this flag is given. -R Set the resistance threshold to infinity. -S symfile Each line in the file symfile is of the form sym=value, just like the argument to the -s flag above; the lines are interpreted in the same fashion. (This option is not currently used by extcheck, but it is common to ext2sim et. al.) -T tech Set the technology in the output .sim file to tech. This overrides any technology specified in the root .ext file. SEE ALSO
ext2dlys(1), ext2sim(1), ext2spice(1), magic(1), rsim(1), sim2spice(1), ext(5), sim(5) AUTHOR
Walter Scott BUGS
The -s mechanism is incomplete; it should allow quantities other than transistor lengths and widths to be specified. EXTCHECK(1)

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EXT2SIM(1)						      General Commands Manual							EXT2SIM(1)

ext2sim - convert hierarchical ext(5) extracted-circuit files to flat sim(5) files SYNOPSIS
ext2sim [ -a aliasfile ] [ -l labelsfile ] [ -o simfile ] [ -A ] [ -B ] [ -F ] [ -L ] [ -t ] [ extcheck-options ] [ -y num ] [ -f mit|lbl|su ] [ -J hier|flat ] [ -j device:sdRclass[/subRclass]/defaultSubstrate ] root DESCRIPTION
Ext2sim will convert an extracted circuit from the hierarchical ext(5) representation produced by Magic to the flat sim(5) representation required by many simulation tools. The root of the tree to be extracted is the file root.ext; it and all the files it references are recursively flattened. The result is a single, flat representation of the circuit that is written to the file root.sim, a list of node aliases written to the file, and a list of the locations of all nodenames in CIF format, suitable for plotting, to the file root.nodes. The file root.sim is suitable for use with programs such as crystal(1), esim(1), or sim2spice(1). The following options are recognized: -a aliasfile Instead of leaving node aliases in the file, leave it in aliasfile. -l labelfile Instead of leaving a CIF file with the locations of all node names in the file root.nodes, leave it in labelfile. -o outfile Instead of leaving output in the file root.sim, leave it in outfile. -A Don't produce the aliases file. -B Don't output transistor or node attributes in the .sim file. This option will also disable the output of information such as the area and perimeter of source and drain diffusion and the fet substrate. For compatibitlity reasons the latest version of ext2sim outputs this information as node attibutes. This option is necessary when preparing input for programs that don't know about attributes, such as sim2spice(1) (which is actually made obsolete by ext2spice(1), anyway), or rsim(1). -F Don't output nodes that aren't connected to fets (floating nodes). -L Don't produce the label file. -tchar Trim characters from node names when writing the output file. Char should be either "#" or "!". The option may be used twice if both characters are desired. -f MIT|LBL|SU Select the output format. MIT is the traditional sim(5) format. LBL is a variant of it understood by gemini(1) which includes the substrate connection as a fourth terminal before length and width. SU is the internal Stanford format which is described also in sim(5) and includes areas and perimeters of fet sources, drains and substrates. -y num Select the precision for outputing capacitors. The default is 1 which means that the capacitors will be printed to a precision of .1 fF. -J hier|flat Select the source/drain area and perimeter extraction algorithm. If hier is selected then the areas and perimeters are extracted only within each subcell. For each fet in a subcell the area and perimeter of its source and drain within this subcell are out- put. If two or more fets share a source/drain node then the total area and perimeter will be output in only one of them and the other will have 0. If flat is selected the same rules apply only that the scope of search for area and perimeter is the whole netlist. In general flat (which is the default) will give accurate results (it will take into account shared sources/drains) but hier is provided for backwards compatibility with version 6.4.5. On top of this selection you can individually control how a ter- minal of a specific fet will be extracted if you put a source/drain attribute. ext:aph makes the extraction for that specific terminal hierarchical and ext:apf makes the extraction flat (see the magic tutorial about attaching attribute labels). Addition- aly to ease extraction of bipolar transistors the gate attribute ext:aps forces the output of the substrate area and perimeter for a specific fet (in flat mode only). -j device:sdRclass[/subRclass]/defaultSubstrate Gives ext2sim information about the source/drain resistance class of the fet type device. Makes device to have sdRclass source drain resistance class, subRclass substrate (well) resistance class and the node named defaultSubstrate as its default substrate. The defaults are nfet:0/Gnd and pfet:1/6/Vdd which correspond to the MOSIS technology file but things might vary in your site. Ask your local cad administrator. The way the extraction of node area and perimeter works in magic the total area and perimeter of the source/drain junction is summed up on a single node. That is why all the junction areas and perimeters are summed up on a single node (this should not affect simulation results however). Special care must be taken when the substrate of a fet is tied to a node other than the default substrate (eg in a bootstraping charge pump). To get the correct substrate info in these cases the fet(s) with separate wells should be in their own separate subcell with ext:aph attributes attached to their sensitive terminals (also all the transistors which share sensistive terminals with these should be in another subcell with the same attributes). In addition, all of the options of extcheck(1) are accepted. SCALING AND UNITS
If all of the .ext files in the tree read by ext2sim have the same geometrical scale (specified in the scale line in each .ext file), this scale is reflected through to the output, resulting in substantially smaller .sim files. Otherwise, the geometrical unit in the output .sim file is a centimicron. Resistance and capacitance are always output in ohms and femptofarads, respectively. SEE ALSO
extcheck(1), ext2dlys(1), ext2spice(1), magic(1), rsim(1), ext(5), sim(5) AUTHOR
Walter Scott additions/fixes by Stefanos Sidiropoulos. BUGS
Transistor gate capacitance is typically not included in node capacitances, as most analysis tools compute the gate capacitance directly from the gate area. The -c flag therefore provides a limit only on non-gate capacitance. The areas and perimeters of fet sources and drains work only with the simple extraction algorith and not with the extresis flow. So you have to model them as linear capacitors (create a special extraction style) if you want to extract parasitic resistances with extresis. 4th Berkeley Distribution EXT2SIM(1)

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