AIX and DST


 
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Operating Systems AIX AIX and DST
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Old 03-08-2007
AIX and DST

Just a quick last minute thing here.

AIX 5.1. I ran the perl script referenced in the tutorials and found the AIX box is triggering DST on the 14th instead of the 11th. The 5.2 boxes come back with the right answers. The DST patches have been applied (or I'd have Apr 1st instead of the 14th).

Anyone else seeing this?

AIX 5.1
Code:
Enter val - 1173855599
val = 1173855599
  1173855599  Wed 2007-03-14 01:59:59 Standard Time
  1173855600  Wed 2007-03-14 03:00:00 Daylight Saving Time

AIX 5.2
Code:
Enter val - 1173596399
val = 1173596399
  1173596399  Sun 2007-03-11 01:59:59 Standard Time
  1173596400  Sun 2007-03-11 03:00:00 Daylight Saving Time

Carl
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HWPREFS(1)						    BSD General Commands Manual 						HWPREFS(1)

NAME
hwprefs -- inspect and control low-level system and processor parameters SYNOPSIS
hwprefs [-v] [-h] [cpu_count={1..N}] [cpu_enable {1..N}] [cpu_disable {1..N}] [cpu_l2_cache={true, false}] [cpu_l3_cache={true, false}] [cpu_nap={true, false}] [cpu_hwprefetch={0, 4, 8}] [cpu_nop_dsts={true, false}] [memctl_readbypass={true, false}] [os_class] [os_type] [machine_type] [memory_size] [cpu_type] [cpu_freq] [cpu_bus_freq] [memctl_type] [ioctl_type"] DESCRIPTION
hwprefs inspects and controls low-level system and processor parameters -v verbose mode -h display help message cpu_count={1..N} number of processors available for use by MacOS X cpu_enable {1..N} enable a specific processor cpu_disable {1..N} disable a specific processor cpu_nap={true, false} processor nap cpu_l2_cache={true, false} processor L2 cache cpu_l3_cache={true, false} processor L3 cache cpu_hwprefetch={0, 4, 8} prefetch engines used by hardware prefetcher (PPC970 only): 0 - all prefetch engines disabled, DST instructions treated as NOPs 4 - four automatic hardware prefetch engines, four used by DST instructions 8 - eight automatic hardware prefetch engines, DST instructions treated as NOPs cpu_nop_dsts={true, false} treat DST instructions as nops memctl_readbypass={true, false} memory controller (U3 only) read-bypass optimization (allows read commands to memory to bypass straight to read memory request queue, saving a significant number of cycles) os_class displays OS class {Cheetah, Puma, Jaguar, Smeagol, Panther, Tiger} os_type displays operating system type machine_type displays machine type memory_size displays system memory cpu_type displays processor type and version cpu_freq displays processor clock frequency cpu_bus_freq displays processor bus frequency memctl_type displays memory controller type ioctl_type displays io controller type Darwin December 21, 2005 Darwin