I have a big makefile that I am trying to get my head around, this line is what is confusing me.
I know roughly the purpose of LDFLAGS, but I struggle following the chain of variables in this linker flag expression. It seems like there is unnecessary repetition and that confuses me slightly. I need to modify that makefile to include shared library that the manufacturer of the embedded system has made. The line below is what is only provided in the software manual for that system,
I'd like to include lGSM_Module in the above LDFLAGS variable. I have tried this, but successfully.
I have this program which has lots of source files in the directories
src
src/dir1
src/dir2
src/dir3... and so on
I am trying to understand the following Makefile:
CC = gcc
CFLAGS= -g -c -D_REENTRANT
SOURCES = src/main.c src/dir1/a.c src/dir1/b.c src/dir2/x.c src/dir2/y.c ...and so on... (5 Replies)
Hi, I'm trying to run the module load command in a Makefile and i'm getting the following error:
make: module: command not found
Why is this? Is there any way to run this command in a Makefile?
NOTE: command - module load msjava/sunjdk/1.5.0 works fine outside of the Makefile (2 Replies)
I am able to 'Make' some of projects's modules using GNU's make except one where it throws me the following error
gmake -f Makefile
/bin/sh: syntax error at line 1: `if' unexpected
gmake: *** Error 2
I am sure it has nothing to do with the Makefile as there is no 'if' in the first... (1 Reply)
I have 2 libraries in 2 different directories that I build with Makefiles.
library B depends on library A. If I modify a .cpp file in library A and run lib B's Makefile can I have B's makefile to automatically rebuild library A?
I am now rebuilding A, followed by B... but I'd like B to... (0 Replies)
Use and complete the template provided. The entire template must be completed. If you don't, your post may be deleted!
1. The problem statement, all variables and given/known data:
Basically, the prompt is make a makefile with various sub makefiles in their respective subdirectories. All code... (1 Reply)
Hi,
I am creating a program with the C language that simulates the WC command in Unix. My program needs to count lines, bytes and words. I have not added the code to count bytes and words yet. I am having trouble understanding what the file option/flag '-' does. I can not visualize how it moves... (1 Reply)
Hello,
I have to write makefile which supports specific targets and I have to do the following things:
- A variable T determines whether the function is executed 1 or 2
- A variable N determines which size will be executed
e.g. it must be read from the command line "make 1500" where 1... (0 Replies)
Hi all,
I'm reading the GNU Make book I cannot understand the following syntax from the book.
objects = foo.o bar.o
all : $(objects)
$(objects) : %.o : %.c
$(CC) -c $(CFLAGS) $< -o $@
If I run: make, I get the output:
cc -c foo.c
cc -o foo foo.o
I think I... (3 Replies)
MAKE(1) General Commands Manual MAKE(1)NAME
make - a program for maintaining large programs
SYNOPSIS
make [-f file] [-iknpqrst] [option] ... [target]
OPTIONS -f Use file as the makefile
-i Ignore status returned by commands
-k On error, skip to next command
-n Report, but do not execute
-p Print macros and targets
-q Question up-to-dateness of target
-r Rule inhibit; do not use default rules
-s Silent mode
-t Touch files instead of making them
EXAMPLES
make kernel # Make kernel up to date
make -n -f mfile # Tell what needs to be done
DESCRIPTION
Make is a program that is normally used for developing large programs consisting of multiple files. It keeps track of which object files
depend on which source and header files. When called, it does the minimum amount of recompilation to bring the target file up to date.
The file dependencies are expected in makefile or Makefile , unless another file is specified with -f. Make has some default rules built
in, for example, it knows how to make .s files from .c files. Here is a sample makefile .
d=/user/ast # d is a macro
program: head.s tail.s# program depends on these
cc -o program head.s tail.s# tells how to make program
echo Program done. # announce completion
head.s: $d/def.h head.c # head.s depends on these
tail.s: $d/var.h tail.c # tail.s depends on these
A complete description of make would require too much space here. Many books on UNIX discuss make . Study the numerous Makefiles in the
MINIX source tree for examples.
SEE ALSO cc(1).
MAKE(1)