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Operating Systems AIX AIX understanding memory using Post 303036686 by Phat on Monday 8th of July 2019 06:41:14 AM
Old 07-08-2019
AIX understanding memory using

Hello,

I would like to understand better in AIX memory use
Code:
[root@xxx] / > svmon -G -O unit=MB
Unit: MB
--------------------------------------------------------------------------------------
               size       inuse        free         pin     virtual  available   mmode
memory      9216.00     2325.38     6890.62      896.11     1943.12    6975.40     Ded
pg space   18944.00        8.48

               work        pers        clnt       other
pin          539.12           0        9.23      347.75
in use      1943.12           0      382.26

So I can say that, my total free RAM is : free (2325.38) + available (1943.12) = 4268.5 MB ???
So what are pin/virtual meaning here?
 

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Netlist::Pin(3pm)					User Contributed Perl Documentation					 Netlist::Pin(3pm)

NAME
Verilog::Netlist::Pin - Pin on a Verilog Cell SYNOPSIS
use Verilog::Netlist; ... my $pin = $cell->find_pin ('pinname'); print $pin->name; DESCRIPTION
A Verilog::Netlist::Pin object is created by Verilog::Netlist::Cell for for each pin connection on a cell. A Pin connects a net in the current design to a port on the instantiated cell's module. ACCESSORS
See also Verilog::Netlist::Subclass for additional accessors and methods. $self->cell Reference to the Verilog::Netlist::Cell the pin is under. $self->comment Returns any comments following the definition. keep_comments=>1 must be passed to Verilog::Netlist::new for comments to be retained. $self->delete Delete the pin from the cell it's under. $self->module Reference to the Verilog::Netlist::Module the pin is in. $self->name The name of the pin. May have extra characters to make vectors connect, generally portname is a more readable version. There may be multiple pins with the same portname, only one pin has a given name. $self->net Reference to the Verilog::Netlist::Net the pin connects to. Only valid after a link. $self->netlist Reference to the Verilog::Netlist the pin is in. $self->netname The net name the pin connects to. $self->portname The name of the port connected to. $self->port Reference to the Verilog::Netlist::Port the pin connects to. Only valid after a link. MEMBER FUNCTIONS
See also Verilog::Netlist::Subclass for additional accessors and methods. $self->lint Checks the pin for errors. Normally called by Verilog::Netlist::lint. $self->dump Prints debugging information for this pin. DISTRIBUTION
Verilog-Perl is part of the <http://www.veripool.org/> free Verilog EDA software tool suite. The latest version is available from CPAN and from http://www.veripool.org/verilog-perl <http://www.veripool.org/verilog-perl>. Copyright 2000-2012 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. AUTHORS
Wilson Snyder <wsnyder@wsnyder.org> SEE ALSO
Verilog-Perl, Verilog::Netlist::Subclass Verilog::Netlist perl v5.14.2 2012-05-04 Netlist::Pin(3pm)
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