I am trying to use sed to delete multiple lines in a file. The problem is that I need to search for a certain line and then once found delete it plus the next 4 lines. For instance if I had a file that consisted of the following lines:
#Data1.start
(
(Database= data1)
(Name = IPC)... (1 Reply)
Trying to write a sed command that applies multiple replacements to a specific address. Need a second pair of eyes I guess cause my syntax appears to be correct (obviously not though) I am getting an error. Any Help would be appreciated! Thanks in advance.
sed -f foo envOracle
sed: Function... (2 Replies)
hello!
I have a few sed commands
sed '/^$/d' < $1 > tmp.t
sed '/^ \{3,\}/d' < tmp.t > tmp1.txt
.....
how can I write them in a single line?
sed '/^$/d' < $1 > | '/^ \{3,\}/d' < $1 > tmp1.txt
any idea?
thanks. (5 Replies)
Below an example of what I mean. The first attempt does what I want; the second doesn't, because bash assumes a line break means the end of an individual "command unix". Is there some way that I can convince bash to parse out, eg, to the closing parenthesis?
I'm thinking this would allow for... (1 Reply)
Hi all:
I have a file in which the contents are as following:
...
This is a test
ONE
TWO
Hello, world!
XXX YYY CCC
test again
three, four
five
six
seven
world
AAA BBB QQQ
test
eight, nine
world (3 Replies)
Got another sed question :)
My text block is
I need to do the following:
If (and only if) the line starting with 10002,11 is followed by a line starting with 10004,9 , insert the line 10003,9 between the 2
Thus, my output should be
I tried
but this gives me
(the order... (3 Replies)
Hi,
I want to make sed write a part of fileA (first 7 lines) to file1 and the rest of fileA to file2 in a single call and single line in sed. If I do the following:
sed '1,7w file1; 8,$w file2' fileA
I get only one file named file1 plus all the characters following file1. If I try to use curly... (1 Reply)
Hello I am hoping you may help.
I am not sure how to go about this exactly, I know the tools but not sure how to make them work together.
I have two SED commands that I would like to run in a shell script. I would like to take
the manual input of a user (types in when prompted) to be used... (4 Replies)
Let's say I have a file called test.out. In this file I want to do the following:
1. Search for DIP-10219 and with this:
2. Remove everything in front of cn=
3. Remove everything after *com
4. Remove duplicate lines
5. Replace ( with \(
6. Replace ) with \)
For 1-3 I have figured out this... (11 Replies)
Hi everybody,
I am writing a little script to manage keystores and need some help with sed.
The output of the keystore file is like:
vi 2, Dec 7, 2012, trustedCertEntry,
Certificate fingerprint (MD5): F9:1F:FE:E6:A3:CB:99:88:44:D4:67:ED:G5:F8:97:7A
system@remote-server, Dec 17, 2013,... (13 Replies)
Discussion started by: Hamss
13 Replies
LEARN ABOUT PHP
vst
VST(5) VHDL subset of ASIM/LIP6/CAO-VLSI lab. VST(5)NAME
vst
VHDL structural subset.
ORIGIN
This software belongs to the ALLIANCE CAD SYSTEM developed by the ASIM team at LIP6 laboratory of Universite Pierre et Marie CURIE, in
Paris, France.
Web : http://asim.lip6.fr/recherche/alliance/
E-mail : alliance-users@asim.lip6.fr
DESCRIPTION
This document describes the ALLIANCE VHDL subset for structural descriptions.
The declaration part of a structural description includes signal decalarations and component declarations.
An internal signal can be declared of any type supported by the present VHDL subset except reg_bit and reg_vector.
A component must be declared with exactly the same port description as in its entity specification. This means that local ports are to be
declared with the same name, type and kind and in the same order.
A structural description is a set of component instanciation statements. Instances' ports are connected to each other trough signals in a
port map specification. Both explicit and implicit port map specifications are supported by the ALLIANCE VHDL subset.
The present version of the VHDL compiler does not allow unconnected ports (the open mode is not supported).
Only the concatenation operator (&) can be used in the actual part (effective signal conntected to a formal port) of a port map specifica-
tion.
EXAMPLES
Here is the description of an adder with an accumulator register.
entity add_accu is
port (
clk : in bit;
command : in bit;
data_in : in bit_vector (31 downto 0);
data_out : out bit_vector (31 downto 0);
cry_out : out bit;
vdd : in bit;
vss : in bit
);
end add_accu;
architecture structural of add_accu is
signal eff_data : bit_vector (31 downto 0); -- effective operande
signal adder_out : bit_vector (31 downto 0); -- adder's result
signal accu_out : bit_vector (31 downto 0); -- accumulator
component adder
port (a : in bit_vector (31 downto 0);
b : in bit_vector (31 downto 0);
res : out bit_vector (31 downto 0));
end component;
component and_32
port (a : in bit_vector (31 downto 0);
cmd : in bit;
res : out bit_vector (31 downto 0));
end component;
component falling_edge_reg
port (din : in bit_vector (31 downto 0);
clk : in bit;
dout : out bit_vector (31 downto 0));
end component;
begin
my_adder : adder
port map (a => eff_data, b => accu_out, res => adder_out);
my_mux : and_32
port map (cmd => command, a => accu_out, res => eff_data);
my_reg : falling_edge_reg
port map (din => adder_out, clk => clk, dout => accu_out);
end;
SEE ALSO vhdl(5), vbe(5), asimut(1)BUG REPORT
This tool is under development at the ASIM department of the LIP6 laboratory.
We need your feedback to improve documentation and tools.
ASIM /LIP6 October 1, 1997 VST(5)