DPGEN_RF1(3)						  Alliance - genlib User's Manual					      DPGEN_RF1(3)

NAME

       DPGEN_RF1, DPGEN_RF1R0 - Register File Macro-Generator

SYNOPSIS

       #include  <genlib.h>

       void GENLIB_MACRO (DPGEN_RF1, char *modelname, long flags, long N);

       void GENLIB_MACRO (DPGEN_RF1R0, char *modelname, long flags, long N);

DESCRIPTION

       Generate  a  register file of regNumber words of N bits whitout decoder named modelname. The DPGEN_RF1R0 variant differs from the DPGEN_RF1
       in that the register of address zero is stuck to zero. You can write into it, it will not change the  value.  When  read,  it  will  always
       return zero.

       How it works :

       o datain0 and datain1 : the two write busses. Only one is used to actually write the register word, it is selected by the sel signal.

       o sel : when set to '0' the datain0 is used to write the register word, otherwise it will be datain1.

       o selr, selw : this register file have no decoder, so selr have a bus width equal to regNumber. One bit for each word.

   TERMINAL NAMES
       1. ckok : clock signal (input, 1 bit).

       2. sel : select the write bus (input, 1 bit).

       3. selr : the decoded read address (input, regNumber bits).

       4. selw : the decoded write address (input, regNumber bits).

       5. datain0 :  first write bus (input, N bits).

       6. datain1 :  second write bus (input, N bits).

       7. dataout : read bus (output, N bits).

       8. vdd : power.

       9. vss : ground.

EXAMPLE

       GENLIB_MACRO(DPGEN_RF1, "model_rf1x8_32"
			     , F_BEHAV|F_PLACE
			     , 32  /* Words size.      */
			     , 8   /* Number of words. */
			     );

       GENLIB_LOINS( "model_rf1x8_32"
		   , "instance1_rf1_32"
		   , "ckok"
		   , "sel"
		   , "selr[7:0]"
		   , "selw[7:0]"
		   , "datain0[31:0]"
		   , "datain1[31:0]"
		   , "dataout[31:0]"
		   , "vdd", "vss", NULL
		   );

SEE ALSO

       GENLIB_MACRO(3), genlib(1)

ASIM
/LIP6							   30 July 2004 						      DPGEN_RF1(3)