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The Lounge What is on Your Mind? New Icons Coming from Font Awesome Post 303020949 by Don Cragun on Tuesday 31st of July 2018 10:49:08 PM
Old 07-31-2018
Quote:
Originally Posted by Neo
Hey Don,

Updating the counters are all cron based for performance reasons and so it's unlikely I will make any changes to update counters in real time. To create data base queries to update counters in real time would case a significant performance hit for the site and updating counters in real time is not necessary.
If I hit the thumbs up button and refresh the screen, the counter goes up. If I remove my thanks on that post and refresh the screen again, the counter goes down. All of this occurs is in less than 5 seconds. How often is this cron job running to it make this look like it is happening in real time? Smilie
 

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COUNTER(9)						   BSD Kernel Developer's Manual						COUNTER(9)

NAME
counter -- SMP-friendly kernel counter implementation SYNOPSIS
#include <sys/types.h> #include <sys/systm.h> #include <sys/counter.h> counter_u64_t counter_u64_alloc(int wait); void counter_u64_free(counter_u64_t c); void counter_u64_add(counter_u64_t c, int64_t v); void counter_enter(); void counter_exit(); void counter_u64_add_protected(counter_u64_t c, int64_t v); uint64_t counter_u64_fetch(counter_u64_t c); void counter_u64_zero(counter_u64_t c); #include <sys/sysctl.h> SYSCTL_COUNTER_U64(parent, nbr, name, access, ptr, descr); SYSCTL_ADD_COUNTER_U64(ctx, parent, nbr, name, access, ptr, descr); DESCRIPTION
counter is a generic facility to create counters that can be utilized for any purpose (such as collecting statistical data). A counter is guaranteed to be lossless when several kernel threads do simultaneous updates. However, counter does not block the calling thread, also no atomic(9) operations are used for the update, therefore the counters can be used in any non-interrupt context. Moreover, counter has special optimisations for SMP environments, making counter update faster than simple arithmetic on the global variable. Thus counter is considered suitable for accounting in the performance-critical code pathes. counter_u64_alloc(wait) Allocate a new 64-bit unsigned counter. The wait argument is the malloc(9) wait flag, should be either M_NOWAIT or M_WAITOK. If M_NOWAIT is specified the operation may fail. counter_u64_free(c) Free the previously allocated counter c. counter_u64_add(c, v) Add v to c. The KPI does not guarantee any protection from wraparound. counter_enter() Enter mode that would allow to safely update several counters via counter_u64_add_protected(). On some machines this expands to critical(9) section, while on other is a nop. See IMPLEMENTATION DETAILS. counter_exit() Exit mode for updating several counters. counter_u64_add_protected(c, v) Same as counter_u64_add(), but should be preceded by counter_enter(). counter_u64_fetch(c) Take a snapshot of counter c. The data obtained is not guaranteed to reflect the real cumulative value for any moment. counter_u64_zero(c) Clear the counter c and set it to zero. SYSCTL_COUNTER_U64(parent, nbr, name, access, ptr, descr) Declare a static sysctl oid that would represent a counter. The ptr argument should be a pointer to allocated counter_u64_t. A read of the oid returns value obtained through counter_u64_fetch(). Any write to the oid zeroes it. SYSCTL_ADD_COUNTER_U64(ctx, parent, nbr, name, access, ptr, descr) Create a sysctl oid that would represent a counter. The ptr argument should be a pointer to allocated counter_u64_t. A read of the oid returns value obtained through counter_u64_fetch(). Any write to the oid zeroes it. IMPLEMENTATION DETAILS
On all architectures counter is implemented using per-CPU data fields that are specially aligned in memory, to avoid inter-CPU bus traffic due to shared use of the variables between CPUs. These are allocated using UMA_ZONE_PCPU uma(9) zone. The update operation only touches the field that is private to current CPU. Fetch operation loops through all per-CPU fields and obtains a snapshot sum of all fields. On amd64 a counter update is implemented as a single instruction without lock semantics, operating on the private data for the current CPU, which is safe against preemption and interrupts. On i386 architecture, when machine supports the cmpxchg8 instruction, this instruction is used. The multi-instruction sequence provides the same guarantees as the amd64 single-instruction implementation. On some architectures updating a counter require a critical(9) section. SEE ALSO
atomic(9), critical(9), locking(9), malloc(9), sysctl(9), uma(9) HISTORY
The counter facility first appeared in FreeBSD 10.0. AUTHORS
The counter facility was written by Gleb Smirnoff and Konstantin Belousov. BSD
February 7, 2014 BSD
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