01-10-2018
Non Intel-x86 processors are quite safe.
1. The more reduced the instruction set (RISC) the shorter is the decoding pipeline, and it makes less (or no) sense to prefetch many instructions. That makes attacks much harder if not impossible.
2. An attack will likely aim at x86 CPUs, then comes ARM. And the most feared way is: via a Web browser. You certainly do not run a Web browser on AIX.
No panic.
"old = unsafe" is a myth of the computer industry (guess why).
While "cheap and old = unsafe" is sometimes true (Linux, Windows).
I would not even upgrade AIX, just install the latest patches for the current AIX.
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LEARN ABOUT SUNOS
sync_instruction_memory
sync_instruction_memory(3C) Standard C Library Functions sync_instruction_memory(3C)
NAME
sync_instruction_memory - make modified instructions executable
SYNOPSIS
void sync_instruction_memory(caddr_t addr, int len);
DESCRIPTION
The sync_instruction_memory() function performs whatever steps are required to make instructions modified by a program executable.
Some processor architectures, including some SPARC processors, have separate and independent instruction and data caches which are not
kept consistent by hardware. For example, if the instruction cache contains an instruction from some address and the program then stores a
new instruction at that address, the new instruction may not be immediately visible to the instruction fetch mechanism. Software must
explicitly invalidate the instruction cache entries for new or changed mappings of pages that might contain executable instructions. The
sync_instruction_memory() function performs this function, and/or any other functions needed to make modified instructions between addr and
addr+len visible. A program should call sync_instruction_memory() after modifying instructions and before executing them.
On processors with unified caches (one cache for both instructions and data) and pipelines which are flushed by a branch instruction, such
as the x86 architecture, the function may do nothing and just return.
The changes are immediately visible to the thread calling sync_instruction_memory() when the call returns, even if the thread should
migrate to another processor during or after the call. The changes become visible to other threads in the same manner that stores do; that
is, they eventually become visible, but the latency is implementation-dependent.
The result of executing sync_instruction_memory() are unpredictable if addr through addr+len-1 are not valid for the address space of the
program making the call.
RETURN VALUES
No values are returned.
ATTRIBUTES
See attributes(5) for descriptions of the following attributes:
+-----------------------------+-----------------------------+
| ATTRIBUTE TYPE | ATTRIBUTE VALUE |
+-----------------------------+-----------------------------+
|MT-Level |MT-Safe |
+-----------------------------+-----------------------------+
SEE ALSO
attributes(5)
SunOS 5.10 12 Feb 1997 sync_instruction_memory(3C)