I think you mix up two different things: shell scripts and makefiles.
Makefiles (more precisely: the
make-utility) work rule-based, so you don't need explicit conditionals - everything is a conditional anyway.
make works like that: you define so-called "dependencies" between files: i.e. you have three object files where each depends on a single source file. Whenever one of the source file changes the corresponding object file has to be generated anew. This is done by executing the code in the rule-definition. For every dependency you can create a rule, but usually you create rules for groups of dependencies: whenever ".c" (the source) changes, the corresponding ".obj" (the object) has to be generated and the rule for this is to call the compiler to compile exactly the one source-file. For this there are "make-variables" like "$@", "$<", etc., which are filled with the name(s) of the files involved in the rule. See the man-page of
make for details.
You can also create cascades of these rules: you base
.obj-files on
.c-files and you base executables on the
.obj-files. So, when a source file changes, the corresponding object is generated and in turn this leads to the executable being generated too (by calling the linker to link all the objects to the executable.
You might want to read
this little introduction i once wrote.
I hope this helps.
bakunin