Hi All,
I have a file that I need to be able to find a pattern match on a line, search that line for a text pattern, and replace that text.
An example of 4 lines in my file is:
1. MatchText_randomNumberOfText moreData ReplaceMe moreData
2. MatchText_randomNumberOfText moreData moreData... (4 Replies)
script is as below
v_process_run=5
typeset -i p_cnt=0
pdata=/home/proc_data.log
while
do
# execute script in background
dummy_test.sh "a1" "a2" &
p_cnt=$p_cnt+1
echo "data : $p_cnt : Y" >> $pdata
done
file created with following data in... (1 Reply)
I have a text file with following content (3 lines)
filename : output.txt
first line:12/12/2008
second line:12/12/2008
third line:Y
I would like to know how we can replace 'Y' with 'N' in the 3rd line keeping 1st and 2nd lines same as what it was before.
I tried using cat output.txt... (4 Replies)
I have 100+ python files in a single directory. I need to replace a specific path occurrence with a variable name.
Following are the find and the replace strings:
Findstring--"projects\\Debugger\\debugger_dp8051_01\\debugger_dp8051_01.cywrk"
Replacestring--self.projpath
I tried... (5 Replies)
Hello,
I am trying to search and replace but I don't know how to do it. My simple knowlegde in search and replace using sed is not helping me at all.
File:
its a cause value #22: dfg ggg
Cause value #1: aasfa fasdf
asfa value #22: affg gggg
Basically i want to replace the... (6 Replies)
Hi all,
I have output files that are all text files with various different extensions.
So, if I submit the input file "job_name.inp", when it finishes I get an output file "job_name.dat". A typical input file looks something like this:
$CONTRL SCFTYP=RHF RUNTYP=ENERGY MAXIT=199 MULT=1... (4 Replies)
Hi
I am trying to search for a particular occurrence of a string in a file, and if found, append another string to the end of that line.
Here is my file contents:
column1 userlist default nowrite=3 output=4
column2 access default nowrite=3
Here is the code:
A="user=1... (1 Reply)
HI
I have property files having content
QA_server_name=10.232.54.7
QA_port_number=18000
DEV_server_name=10.235.60.73
DEV_port_number=18000
and a .jason file having content like this
{
"server":"localhost"
"port":"17000"
------
}
I will get the parameter... (1 Reply)
Hi,
I have gigabytes of text files that I need to search for "&" and replace with "&". Is there a way to do this efficiently (like sed command)?
Hope you could help.
Thanks. (17 Replies)
I have file .
cat hello.txt
Hello World
I would like to append a string "Today " so the output is
cat hello.txt
Hello World Today
I dont know which line number does the "Hello World" appears otherwise I could have used the Line number to search and append . (3 Replies)
Discussion started by: gubbu
3 Replies
LEARN ABOUT MOJAVE
vst
VST(5) VHDL subset of ASIM/LIP6/CAO-VLSI lab. VST(5)NAME
vst
VHDL structural subset.
ORIGIN
This software belongs to the ALLIANCE CAD SYSTEM developed by the ASIM team at LIP6 laboratory of Universite Pierre et Marie CURIE, in
Paris, France.
Web : http://asim.lip6.fr/recherche/alliance/
E-mail : alliance-users@asim.lip6.fr
DESCRIPTION
This document describes the ALLIANCE VHDL subset for structural descriptions.
The declaration part of a structural description includes signal decalarations and component declarations.
An internal signal can be declared of any type supported by the present VHDL subset except reg_bit and reg_vector.
A component must be declared with exactly the same port description as in its entity specification. This means that local ports are to be
declared with the same name, type and kind and in the same order.
A structural description is a set of component instanciation statements. Instances' ports are connected to each other trough signals in a
port map specification. Both explicit and implicit port map specifications are supported by the ALLIANCE VHDL subset.
The present version of the VHDL compiler does not allow unconnected ports (the open mode is not supported).
Only the concatenation operator (&) can be used in the actual part (effective signal conntected to a formal port) of a port map specifica-
tion.
EXAMPLES
Here is the description of an adder with an accumulator register.
entity add_accu is
port (
clk : in bit;
command : in bit;
data_in : in bit_vector (31 downto 0);
data_out : out bit_vector (31 downto 0);
cry_out : out bit;
vdd : in bit;
vss : in bit
);
end add_accu;
architecture structural of add_accu is
signal eff_data : bit_vector (31 downto 0); -- effective operande
signal adder_out : bit_vector (31 downto 0); -- adder's result
signal accu_out : bit_vector (31 downto 0); -- accumulator
component adder
port (a : in bit_vector (31 downto 0);
b : in bit_vector (31 downto 0);
res : out bit_vector (31 downto 0));
end component;
component and_32
port (a : in bit_vector (31 downto 0);
cmd : in bit;
res : out bit_vector (31 downto 0));
end component;
component falling_edge_reg
port (din : in bit_vector (31 downto 0);
clk : in bit;
dout : out bit_vector (31 downto 0));
end component;
begin
my_adder : adder
port map (a => eff_data, b => accu_out, res => adder_out);
my_mux : and_32
port map (cmd => command, a => accu_out, res => eff_data);
my_reg : falling_edge_reg
port map (din => adder_out, clk => clk, dout => accu_out);
end;
SEE ALSO vhdl(5), vbe(5), asimut(1)BUG REPORT
This tool is under development at the ASIM department of the LIP6 laboratory.
We need your feedback to improve documentation and tools.
ASIM /LIP6 October 1, 1997 VST(5)