?xml version="1.0" ?>
<component id="root" name="root">
    <component id="system" name="system">
        <param name="number_of_A" value="8"/>
        <param name="number_of_B" value="0"/>
        <param name="number_of_C" value="0"/>
        <param name="number_of_D" value="4"/> <!-- This number means how many L2 clusters in each cluster there can be multiple banks/ports -->
        <param name="number_of_E" value="0"/> <!-- This number means how many L3 clusters -->
        <param name="number_of_F" value="1"/>
        <param name="homogeneous_G" value="1"/><!--1 means homo -->
        <param name="homogeneous_H" value="1"/>
       <component id="system.core0" name="core0">
             <param name="RAS_size" value="32"/>                        
            <!-- general stats, defines simulation periods;require total, idle, and busy cycles for senity check  -->
            <!-- please note: if target architecture is X86, then all the instrucions refer to (fused) micro-ops -->
               <stat name="total_instructions" value="3765298576.0"/> <!-- CONX -->
               <stat name="N" value="3700000000.0"/> 
               <stat name="fp_instructions" value="64312000.0"/> 
            <stat name="branch_instructions" value="0"/>
            <stat name="branch_mispredictions" value="0"/>
               <stat name="load_instructions" value="1129589573.0"/> 
               <stat name="store_instructions" value="376529857.6"/> 
               <stat name="committed_instructions" value="3765298576.0"/>
               <stat name="committed_int_instructions" value="3700986576.0"/>
               <stat name="committed_fp_instructions" value="64312000.0"/> 
            <stat name="pipeline_duty_cycle" value="0.6"/>
            <stat name="L" value="100000"/>
            <stat name="idle_cycles" value="0"/>
            <stat name="busy_cycles"  value="100000"/>
            <stat name="ROB_reads" value="263886"/>
            <stat name="ROB_writes" value="263886"/>
            
            <stat name="rename_accesses" value="263886"/>
            <stat name="fp_rename_accesses" value="263886"/>
            
            <stat name="inst_window_reads" value="263886"/>
            <stat name="inst_window_writes" value="263886"/>
            <stat name="inst_window_wakeup_accesses" value="263886"/>
            <stat name="fp_inst_window_reads" value="263886"/>
            <stat name="fp_inst_window_writes" value="263886"/>
            <stat name="fp_inst_window_wakeup_accesses" value="263886"/>
            <!--  RF accesses -->
            <stat name="int_regfile_reads" value="1600000"/>
            <stat name="float_regfile_reads" value="40000"/>
            <stat name="int_regfile_writes" value="800000"/>
            <stat name="float_regfile_writes" value="20000"/>
            
            <stat name="function_calls" value="5"/>
            <stat name="context_switches" value="260343"/>
          
               <stat name="M" value="753059715.3"/> 
               <stat name="fpu_accesses" value="57880800.0"/> 
               <stat name="mul_accesses" value="57880800.0"/>
            <stat name="cdb_alu_accesses" value="1000000"/>
            <stat name="cdb_mul_accesses" value="0"/>
            <stat name="cdb_fpu_accesses" value="0"/>