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Special Forums UNIX and Linux Applications Infrastructure Monitoring CPU - Interrupts distribution Post 302934588 by r_t_1601 on Monday 9th of February 2015 02:19:29 AM
Old 02-09-2015
Also captured the yeild for
Code:
cat /proc/interrupts

Code:
           CPU0,    CPU1,     CPU2,     CPU3,   CPU4,    CPU5,  CPU6,    CPU7,    CPU8,    CPU9,    CPU10,      CPU11,  CPU12,    CPU13,    CPU14,   CPU15,
130:00:00,  1048,       0,      0,       0,       0,      0,       0,       0,       0,       0,        0,  202064668,       0,        0,        0, 512532716, PCI-MSI, eth0 
185:00:00, 5385, 3181749, 3266781, 1267992, 3453589, 2981991, 104657, 265, 0, 66125, 10136, 85428, 2100126, 1341219, 65914, 0, IO-APIC-level, lpfc
193:00:00, 4453, 3421072, 3176832, 975485, 2866437, 3487992, 302016, 29507, 0, 960, 67873, 100243, 1338298, 2182582, 0, 0, IO-APIC-level, lpfc
201:00:00, 7326, 21563193, 12967850, 1946063, 0, 62303, 5370651, 543112, 0, 3329977, 14479511, 65730, 0, 19, 12861008, 20370, IO-APIC-level, megasas
NMI:, 323299, 99906, 73879, 61131, 266359, 91899, 75309, 61200, 102974, 104665, 80748, 104176, 98485, 119343, 91712, 114415, , 
LOC:, 4155248420, 4155248563, 4155248841, 4155248725, 4155248852, 4155248711, 4155249174, 4155249117, 4155248301, 4155247903, 4155248172, 4155248183, 4155248709, 4155248296, 4155248535, 4155248532,

saw uneven
distribution for CPU 0 , CPU 11 and CPU 15 , can anyone suggest if this normal behaviour ?

Last edited by r_t_1601; 02-09-2015 at 07:43 AM..
 

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APIC(4) 						   BSD Kernel Interfaces Manual 						   APIC(4)

NAME
apic -- Advanced Programmable Interrupt Controller (APIC) driver SYNOPSIS
This driver is a mandatory part of amd64 kernel. To compile this driver into i386 or pc98 kernel, place the following line in your kernel configuration file: device apic The following tunable is settable from the loader(8): hint.apic.X.clock controls event timers functionality support. Setting to 0, disables it. Default value is 1. hint.apic.X.disabled Set this to 1 to disable APIC support, falling back to the legacy PIC. DESCRIPTION
There are two components in the Intel APIC system, the local APIC (LAPIC) and the I/O APIC. There is one local APIC in each CPU in the sys- tem. There is typically one I/O APIC for each peripheral bus in the system. Local APICs manage all external interrupts for a specific processor. In addition, they are able to accept and generate inter-processor interrupts (IPIs). I/O APICs contain a redirection table, which is used to route the interrupts they receive from peripheral buses to one or more local APICs. Each local APIC includes one 32-bit programmable timer. This driver uses them to supply kernel with one event timer named "LAPIC". Event timer provided by the driver supports both one-shot an periodic modes. Because of local APIC nature it is per-CPU. The timer frequency is not reported by the platform and so automatically measured by the driver on the first use. Depending on CPU model this timer may stop in C3 and deeper CPU sleep states. Driver automatically adjusts event timer priority and reports it to prevent entering dangerous sleep states when it is used. SEE ALSO
atrtc(4), attimer(4), eventtimers(4), hpet(4) BSD
December 20, 2011 BSD
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