05-20-2014
There is not much that can be learned from truss output in a case like this. No program should ever execute an illegal instruction. When one does, it means the program in question has a bug. If this program usually works ok and this illegal instruction is a rare exception, my guess would be that the program was fed some really screwy data. The program is attempting to process data that it should reject. So I would check the program's input looking for anything really strange.
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LEARN ABOUT ULTRIX
emulate_branch
emulate_branch(3) Library Functions Manual emulate_branch(3)
Name
emulate_branch, execute_branch - branch emulation
Syntax
#include <signal.h>
emulate_branch(scp, branch_instruction)
struct sigcontext *scp;
unsigned long branch_instruction;
execute_branch(branch_instruction)
unsigned long branch_instruction;
Description
The function is passed a signal context structure and a branch instruction. It emulates the branch based on the register values in the
signal context structure. It modifies the value of the program counter in the signal context structure (sc_pc) to the target of the
branch_instruction. The program counter must initially be pointing at the branch and the register values must be those at the time of the
branch. If the branch is not taken the program counter is advanced to point to the instruction after the delay slot (sc_pc += 8).
If the branch instruction is a `branch on coprocessor 2' or `branch on coprocessor 3' instruction, calls to execute the branch in data
space to determine if it is taken or not.
Return Values
The function returns a 0 if the branch was emulated successfully. A non-zero value indicates the value passed as a branch instruction was
not a branch instruction.
The function returns non-zero on taken branches and zero on non-taken branches.
Restrictions
Since is only intended to be used by it does not check its parameter to see if in fact it is a branch instruction. It is really a stop gap
in case a coprocessor is added without the kernel fully supporting it (which is unlikely).
See Also
cacheflush(2), sigvec(2), signal(3)
RISC emulate_branch(3)