You need a generalized rule for how to get from a "source" file to an "object" file. If your source files carry the extension ".src" and your objects the extension ".obj" this would be:
Now you only need a special variable which contains only the file name which triggered the rule to use in the action part - and fortunately there is such a thing: "$<". A possible rule would look like:
If the rule is triggered by the file "foo.src" the command executed would be:
You might want to read the man page of the make-utility to learn more about the various special variables you can use. For instance, there is also a variable for the file name that will be the target of the rule: "$@".
C compilers per default write a file "a.out" instead of naming the object like the source file only with the extension replaced by ".obj". You would have to explicitly tell the compiler which name it should use for its output file with the "-o" option if you do not want this default behavior. This is what "$@" is for:
I am sure you will be able to adapt this to your needs with careful study of the man page.
I am attempting to set-up a Makefile to use for a new system on a Sun Unix machine.
I am new to creating Makefiles. I am trying to start simply by compiling a program. I am getting the following error message but an uncertain what 'Error Code 1' is. Is there a web site with Error Codes... (1 Reply)
I'm trying to do string replacement with a Makefile and this is my scenario:
Inside file "fileA", I have "#include<text>" statements and I want to replace it with the text inside a file called "params". I wish to perform this task using Makefiles. I've tried using m4 but that only works if... (1 Reply)
At my company, we build some stuff using a makefile. While the makefile script is running, a developer may check in a newer version of a source file. The problem is, when we next run the make command, the target file isn't rebuilt, because the date of the target is after the dependency.
Any... (1 Reply)
Hi All
I need to parse the target
something like:
ifeq '$@' 'first'
echo 1 $@
endif
ifeq '$@' 'second'
echo 2 $@
endif
The thing is to be able compare the target string to any string and then do the commands
Thanks a lot
ziv (0 Replies)
Hi all,
I've a makefile which has this line:
@touch $@
I know $@ is for representing the target. But I don't know what's the @ preceding the touch.
Can anyone help me?
Thanks in advance. (4 Replies)
Hello, I'm trying to use the make command with a makefile I've made for an assignment. The professor supplied the code and I've copied it into a new file. I made sure to place the tabs in the correct spaces, however when I try to execute it in UNIX I get:
"make: Fatal error in reader:... (5 Replies)
Hi all,
In a makefile I would like to grab the first line of a given parameter file using ‘head' and assign it to a variable, how do I do this?
I've got a simple makefile but it does not work?
#! /bin/ksh
...
.sqc.c:
db2prep $*.sqc bindfile
if ] DB2_PARM=`/usr/bin/head -1 $*.prm`; fi... (2 Replies)
Hi,
I wanted to know whether there is any way to specify in a makefile how to compile sources from a directory directly by giving the directory path name instead of mentioning each and every source file name.
Regards,
Anil (1 Reply)
Hi!
I've got a build process where scripts create multiple targets from their sources. But here I'm running into a conceptual problem of GNU make: If one has multiple targets in a dependency, make applies the rules once for every target that is out of sync - which is correct for normal... (3 Replies)
hello, I'm trying to create a makefile to run multiple c files. I am able to run one c file only with the code I have when I tried to run 2 or more c files I'm not able. here is my code
# $Source: /home/hectormasencio/make/Makefile,v $
# $Date: 2012/11/27 11:35:30 $
CC= gcc
OBJS= temp.o... (3 Replies)
Discussion started by: Hector M.
3 Replies
LEARN ABOUT XFREE86
gccmakedep
gccmakedep(1) General Commands Manual gccmakedep(1)NAME
gccmakedep - create dependencies in makefiles using 'gcc -M'
SYNOPSIS
gccmakedep [ -sseparator ] [ -fmakefile ] [ -a ] [ -- options -- ] sourcefile ...
DESCRIPTION
The gccmakedep program calls 'gcc -M' to output makefile rules describing the dependencies of each sourcefile, so that make(1) knows which
object files must be recompiled when a dependency has changed.
By default, gccmakedep places its output in the file named makefile if it exists, otherwise Makefile. An alternate makefile may be speci-
fied with the -f option. It first searches the makefile for a line beginning with
# DO NOT DELETE
or one provided with the -s option, as a delimiter for the dependency output. If it finds it, it will delete everything following this up
to the end of the makefile and put the output after this line. If it doesn't find it, the program will append the string to the makefile
and place the output after that.
EXAMPLE
Normally, gccmakedep will be used in a makefile target so that typing 'make depend' will bring the dependencies up to date for the make-
file. For example,
SRCS = file1.c file2.c ...
CFLAGS = -O -DHACK -I../foobar -xyz
depend:
gccmakedep -- $(CFLAGS) -- $(SRCS)
OPTIONS
The program will ignore any option that it does not understand, so you may use the same arguments that you would for gcc(1), including -D
and -U options to define and undefine symbols and -I to set the include path.
-a Append the dependencies to the file instead of replacing existing dependencies.
-fmakefile
Filename. This allows you to specify an alternate makefile in which gccmakedep can place its output. Specifying "-" as the file
name (that is, -f-) sends the output to standard output instead of modifying an existing file.
-sstring
Starting string delimiter. This option permits you to specify a different string for gccmakedep to look for in the makefile. The
default is "# DO NOT DELETE".
-- options --
If gccmakedep encounters a double hyphen (--) in the argument list, then any unrecognized arguments following it will be silently
ignored. A second double hyphen terminates this special treatment. In this way, gccmakedep can be made to safely ignore esoteric
compiler arguments that might normally be found in a CFLAGS make macro (see the EXAMPLE section above). -D, -I, and -U options
appearing between the pair of double hyphens are still processed normally.
SEE ALSO gcc(1), make(1), makedepend(1).
AUTHOR
gccmakedep was written by the XFree86 Project based on code supplied by Hongjiu Lu.
Colin Watson wrote this manual page, originally for the Debian Project, based partly on the manual page for makedepend(1).
XFree86 Version 4.7.0 gccmakedep(1)