Very good introduction! Thank you!
While I was reading a similar instruction about Makefile from LQ forum(http://www.linuxquestions.org), I have a confusion about two Makefile examples :
Makefile1:
Code:
all: temp.txt
temp.txt: target
@echo "temp.txt has been created."
target: dep3
echo $(string) >> temp.txt
@echo "That's all I can tell you right now." >> temp.txt
# and let's mix 'em up a bit...
dep1:
@echo "My name is 'echo'" >> temp.txt
dep3:dep2
@echo "if you don't mind my asking." >> temp.txt
@echo >> temp.txt
dep2:dep1
@printf "What are you doing? " >> temp.txt
# this tag/target will run when we type 'make clean'
clean:
@rm temp.txt
Makefile2:
Code:
string = "I'm doing something!"
all: temp.txt
@echo "temp.txt has been created."
temp.txt:
@echo "My name is 'echo'" >> temp.txt
@printf "What are you doing? " >> temp.txt
@echo "if you don't mind my asking." >> temp.txt
@echo >> temp.txt
@echo $(string) >> temp.txt
@echo "That's all I can tell you right now." >> temp.txt
clean:
@rm temp.txt
After I run make several times, Makefile1 will create temp.txt file of multiple lines, i.e. contents accumulated accordingly.
My confusion is Makefile2 does not give the same result, i.e. I ran make several times, the content of temp.txt does NOT accumulate!
The author stated:
Code:
Why didn't the make file keep writing strings into the file this time?
[Once the file existed there was nothing more that needed to be done for the 'rule' governing temp.txt.]
which seems unclear to me, as both will create temp.txt at the first "make". Could you explain it for me? I think I missed a very important point about Makefile.
According to the same article, I modified Makefile2 and removed the line below all: @echo "temp.txt has been created."
Makefile3:
Code:
string = "I'm doing something!"
all: temp.txt
temp.txt:
@echo "My name is 'echo'" >> temp.txt
@printf "What are you doing? " >> temp.txt
@echo "if you don't mind my asking." >> temp.txt
@echo >> temp.txt
@echo $(string) >> temp.txt
@echo "That's all I can tell you right now." >> temp.txt
clean:
@rm temp.txt
and tried to run make:
Code:
make #fine, temp.txt created
make #Error, or warning:
make: Nothing to be done for 'all'.
My understanding for this third (and the 2nd) example is, temp.txt has been created, so that any "make" will not do the job once temp.txt is there. Am I correct? But in Makefile1 the temp.txt is also there? I must have missed one rule of Makefile.
Thanks a lot!
I am new to creating makefiles.
I have several fortran programs in a folder called as "test" and also have several subroutines in another folder (which is inside this test folder) called as libry
My makefile is in the folder "test"
I want to create a makefile which can access the files in... (2 Replies)
Hi, I'm trying to run the module load command in a Makefile and i'm getting the following error:
make: module: command not found
Why is this? Is there any way to run this command in a Makefile?
NOTE: command - module load msjava/sunjdk/1.5.0 works fine outside of the Makefile (2 Replies)
I have 2 libraries in 2 different directories that I build with Makefiles.
library B depends on library A. If I modify a .cpp file in library A and run lib B's Makefile can I have B's makefile to automatically rebuild library A?
I am now rebuilding A, followed by B... but I'd like B to... (0 Replies)
Use and complete the template provided. The entire template must be completed. If you don't, your post may be deleted!
1. The problem statement, all variables and given/known data:
Basically, the prompt is make a makefile with various sub makefiles in their respective subdirectories. All code... (1 Reply)
Use and complete the template provided. The entire template must be completed. If you don't, your post may be deleted!
1. The problem statement, all variables and given/known data:
I have been trying to make the program swap but i have been getting errors with the makefile such as
driver.o:... (1 Reply)
I'm really confused how to use a makefile.
Are you supposed to be make a file from emacs called MakeFile and put code in there to compile?
I am trying to create a makefile to compile two .cpp files in my current directory to produce two .o files and then link them...
What I did was make a... (1 Reply)
Dear all,
I have a quite simple question about how to manipulate "makefile.am". I intend to:
1. "CFLAGS" and "CXXFLAGS" have no value at all. I know that these values get "-g -O2" by default. On the other hand, when I try to set them as "CFLAGS = " in "makefile.am", I get warning messages... (4 Replies)
Hey everybody,
This may be stup*d question for you, but i am new in unix and i wonder how can i make the rules for translating and linking my .c "primjer1.c", "primjer2.c" and "primjer3.c" in makefile.
Thank you. (7 Replies)
Hi All,
We have moved our OS from Sun Solaris to Linux and also some of the compilers.
Our old makefile used to be as below:
CC=cc
FLAGS=-G -KPIC -DLG_SOLARIS_OS
DEFINES=-DSunOS
SYSLIBS=-lc
.SUFFIXES : .c
.c.o : ;$(CC) -c $(FLAGS) $(DEFINES) $*.c -o $*.o
... (3 Replies)