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Full Discussion: Solaris SPARC speed issue
Operating Systems Solaris Solaris SPARC speed issue Post 302698705 by Pug on Monday 10th of September 2012 06:40:33 PM
Old 09-10-2012
Again, thank you for your responses.

So please let me clarify a few points to be sure.

1. 'hergp' is saying that if the issue is that they are using a T1 T2 type multi core SPARC than the issue is not so much the 32 vs 64 bit compile as it is the single threaded vs multi-threaded processing. Correct?
On Windows x86 vs X64 we found that the increase in compiling to X64 is just under 20% (comparing the running of one process on the same input data). Would you expect something similar on SPARC?

2. 'jlliagreis' saying that if it is possible to design our program to be multi-threaded (which I don't think we can) or if we run the program in parallel processes on different sets of data instead of in sequence, then we should be able to see some improvement. However, the amount will depend on the type of bottle neck we are experiencing (which we do not know yet). So for example, if it is straight CPU bound then we should see the best improvement, whereas if it is I/O bound then they may be less improvement, etc.

3. How do I know if we are running T1 or T2 with regard to floating point? I noticed that you said it is niagara based on the sun4v. How do I tell what T level they have?

4. What Solaris SPARC hardware would be better for doing this type of processing? I am not sure we have a choice but I am certainly curious.

---------- Post updated at 04:40 PM ---------- Previous update was at 09:38 AM ----------

One other things. They have two servers. One is a T2 and the other a T3 and specifically they are:SunOS 5.10 Generic_147440-09 sun4u sparc SUNW,Sun-Fire-V245 (T2)
SunOS 5.10 Generic_147440-01 sun4v sparc sun4v (T3)

What does this tell us about single thread / multi-thread or floating point etc?
How does sun4v differ from sun4u? How does T2 differ from T3?

Thank you.
 

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isalist(5)						Standards, Environments, and Macros						isalist(5)

NAME
isalist - the native instruction sets known to Solaris software DESCRIPTION
The possible instruction set names returned by isalist(1) and the SI_ISALIST command of sysinfo(2) are listed here. The list is ordered within an instruction set family in the sense that later names are generally faster then earlier names; note that this is in the reverse order than listed by isalist(1) and sysinfo(2). In the following list of values, numbered entries generally represent increasing performance; lettered entries are either mutually exclusive or cannot be ordered. This feature is obsolete and may be removed in a future version of Solaris. The lists below do not reflect all the extensions that have been made by modern processors. See getisax(2) for a better way to handle instruction set extensions. SPARC Platforms Where appropriate, correspondence with a given value of the -xarch option of Sun's C 4.0 compiler is indicated. Other compilers might have similar options. 1a. sparc Indicates the SPARC V8 instruction set, as defined in The SPARC Architecture Manual, Version 8, Prentice-Hall, Inc., 1992. Some instructions (such as integer multiply and divide, FSMULD, and all floating point operations on quad operands) can be emulated by the kernel on certain systems. 1b. sparcv7 Same as sparc. This corresponds to code produced with the -xarch=v7 option of Sun's C 4.0 compiler. 2. sparcv8-fsmuld Like sparc, except that integer multiply and divide must be executed in hardware. This corresponds to code pro- duced with the -xarch=v8a option of Sun's C 4.0 compiler. 3. sparcv8 Like sparcv8-fsmuld, except that FSMULD must also be executed in hardware. This corresponds to code produced with the -xarch=v8 option of Sun's C 4.0 compiler. 4. sparcv8plus Indicates the SPARC V8 instruction set plus those instructions in the SPARC V9 instruction set, as defined in The SPARC Architecture Manual, Version 9, Prentice-Hall, 1994, that can be used according to The V8+ Technical Specification. This corresponds to code produced with the -xarch=v8plus option of Sun's C 4.0 compiler. 5a. sparcv8plus+vis Like sparcv8plus, with the addition of those UltraSPARC I Visualization Instructions that can be used according to The V8+ Technical Specification. This corresponds to code produced with the -xarch=v8plusa option of Sun's C 4.0 compiler. 5b. sparcv8plus+fmuladd Like sparcv8plus, with the addition of the Fujitsu SPARC64 floating multiply-add and multiply-subtract instruc- tions. 6. sparcv9 Indicates the SPARC V9 instruction set, as defined in The SPARC Architecture Manual, Version 9, Prentice-Hall, 1994. 7a. sparcv9+vis Like sparcv9, with the addition of the UltraSPARC I Visualization Instructions. 7b. sparcv9+vis2 Like sparcv9, with the addition of the UltraSPARC III Visualization Instructions. 7c. sparcv9+fmuladd Like sparcv9, with the addition of the Fujitsu SPARC64 floating multiply-add and multiply-subtract instructions. x86 Platforms 1. i386 The Intel 80386 instruction set, as described in The i386 Microprocessor Programmer's Reference Manual. 2. i486 The Intel 80486 instruction set, as described in The i486 Microprocessor Programmer's Reference Manual. (This is effectively i386, plus the CMPXCHG, BSWAP, and XADD instructions.) 3. pentium The Intel Pentium instruction set, as described in The Pentium Processor User's Manual. (This is effectively i486, plus the CPU_ID instruction, and any features that the CPU_ID instruction indicates are present.) 4. pentium+mmx Like pentium, with the MMX instructions guaranteed present. 5. pentium_pro The Intel PentiumPro instruction set, as described in The PentiumPro Family Developer's Manual. (This is effectively pentium, with the CMOVcc, FCMOVcc, FCOMI, and RDPMC instructions guaranteed present.) 6. pentium_pro+mmx Like pentium_pro, with the MMX instructions guaranteed present. 7. amd64 The AMD Opteron instruction set, as described in the AMD64 Architecture Programmer's Manual. SEE ALSO
isalist(1), getisax(2), sysinfo(2) SunOS 5.11 20 Mar 2008 isalist(5)
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