Due to strict policies regarding cheating, I can't tell you exactly, but I'll give an example with the undergrad project I made for a course about data structures.

I had the files

Code:

binsearch.c  
bubble.c  
csbubble.c  
heap.c  
hybrid.c  
intsearch.c  
main.c  
Makefile  
quick.c  
sel.c

All .c files but main.c were sorting and finding algorithms. The main.c was obviously the main program which took the measurements and the Makefile is the, well, makefile.

I wrote this:

Code:

CC    = gcc
DEBUG    = NO_DEBUG
CFLAGS    = -ggdb -std=c99 -pedantic -Wall -W -Wshadow -Wpointer-arith -Wconversion -D$(DEBUG)
OBJ    = bubble.o csbubble.o quick.o heap.o hybrid.o binsearch.o intsearch.o sel.o

all:    $(OBJ)
    $(CC) $(CFLAGS)  -lm -o main main.c $(OBJ)

clean:
    rm -f        \
    Makefile~    \
    bubble.c~    \
    bubble.o    \
    csbubble.c~    \
    csbubble.o    \
    quick.c~    \
    quick.o        \
    heap.c~        \
    heap.o        \
    hybrid.c~    \
    hybrid.o    \
    binsearch.c~    \
    binsearch.o    \
    intsearch.c~    \
    intsearch.o    \
    sel.c~        \
    sel.o        \
    main.c~        \
    main        \
    core

The CC variable is the compiler name. Set it to cc or gcc.
The DEBUG will set a define flag, forget it
the CFLAGS are the options to the compiler. You will have your own. The most common ones are -W or -Wall, -ggdb if you want debug symbols, --std=c99 sets the language dialect (forget it), -pedantic rejects extensions (like gnu89), the -D(DEBUG) passes the aforementioned DEBUG symbol which you won't use, and the other -Wx flags just forget them.
OBJ variable containes ALL the object code binaries that the main program needs, ie all intermediary files of compilations of bubble.c, csbubble.c etc. ATTENTION: If you forget to include even a single object file, your make will fail! Include all your .c files but main.c with the .o extension, as I did.

Let's focus at the rest lines:
The first field is the target. It's called "all", followed by a colon. If you type "make all", this target will be activated. After a TAB, there is the list of all dependencies. There you will put ANY object file your program will need, that is the $OBJ (either type $OBJ or $(OBJ) doesn't matter).

After these dependencies are satisfied, the next lines will execute, up until the next target.
Make will find no bubble.o So it will compile bubble.c with $CFLAGS to get bubble.o. Then will find no csbubble.o, and it will compile csbubble.c, etc. There is NO NEED to put a target for each .c file, as many students do. Make knows how to invoke gcc.

When Make finishes, it will proceed with the next line.
There it calls the compiler ($CC) with $CFLAGS to compile main.c and link it against the object files ($OBJ) and the math library (-lm, you won't need that). The -o main means "the output will be called main. If you don't specify it, it defaults to a.out (assembler output, for the history).

Next will find the clean: target and stop.

If you invoke make as "make clean", then this target will be fired.
Here I delete all backup files (*~) all object files (*.o), the main executable and core dump (forget this).
You could just put "rm -f *.o helloworld"

That's all folks!