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Full Discussion: Virtualize x86 on Sparc ?
Operating Systems Solaris Virtualize x86 on Sparc ? Post 302525537 by Tex-Twil on Friday 27th of May 2011 04:12:33 AM
Old 05-27-2011
Virtualize x86 on Sparc ?

Hello,
is it somehow possible to run a x86 Linux OS in a virtual machine in Solaris running on Sparc ? Virtualbox ? Containers ?

I know it would be easier just get a Intel hardware and run the Linux but I might be in a scenario where only Sparc hardware is allowed by corporate policy and still there is a need to run a Linux.

cheers,
Tex
 

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MCE-INJECT(8)						  Linux's Administrator's Manual					     MCE-INJECT(8)

NAME
mce-inject - Inject machine checks into x86 kernel for testing SYNOPSIS
mce-inject mce-file1 ... mce-inject < mce-file DESCRIPTION
mce-inject allows to inject machine checks in a running x86 Linux kernel. machine checks are internal CPU errors. This tool is intended to test the machine check handling code. The injection only happens on the software level and does not simulate full machine check handling on the platform level. The machine checks to be injected are described in a input language similar to the format the kernel outputs on a panic message (with a few extension). In general you should be able to pipe in a panic message to inject that mce. See the IA32 SDM Vol3a chapter 14 for the details on fields. They correspond to the machine check MSRs of the standard IA32 Machine check architecture described there. INPUT LANGUAGE
These generally represent the similarly CPU MSRs, with some metadata on where to inject the exception. Please see the IA software develop- ers Manual for more details. The machine check always starts with MCE or CPU number|broadcast [bank-number] Machine check is injected on CPU xx or broadcasted to all CPUs BANK bank-number Machine check bank to inject on. STATUS {number|fatal|corrected|uncorrected|pcc|uc|val|en|over|ar|ucna|srao|srar|s} The symbols generally represent hardware register bits, as documented in the Intel software developer's manual. When multiple are listed they are ored together. MCGSTATUS {number|mcip|ripv|eipv} The symbols generally represent hardware register bits, as documented in the Intel software developer's manual. When multiple are listed they are ored together. ADDR number RIP number RIP number:<number>{string} RIP number:number MISC number CPU number : machine check exception : number BANK number : number parsed for compatibility with kernel output. Use explicit statements TSC number TSC state injected in machine check NOBROADCAST Don't broadcast exceptions to all CPUs. Default is to broadcast UC IRQBROADCAST Broadcast IRQ to all CPUs that not getting error injection. NMIBROADCAST Broadcast NMI to all CPUs that not getting error injection. IN_IRQ MCE should be injected in interrupt context IN_PROC MCE injected in process context. HOLD Don't inject MCE immediately but hold it for later injection. This is useful for testing injection on multiple CPUs in parallel SOCKETID number Socketid. Ignored by kernel on injection. MCGCAP number Machine check capabilities register value. Currently ignored by kernel on injection. POLL Inject in machine check poller code. EXCP Inject as machine check exception. APICID number APIC ID of CPU. Ignored by kernel on injection. A list of symbols ors the symbols together. Multiple fields can be on a line. number can be hex/octal/decimal in the usual C format. Multiple machine checks can be in a single file, each new one starts with "CPU" or "MCE". For all missing fields reasonable default values are filled in (hopefully) Comments start with # until the end of the line The keywords are case-insensitive. REQUIREMENTS
mce-inject to run as root. /dev/mcelog has to exist. The kernels needs to have machine check injection ( CONFIG_X86_MCE_INJECT ) enabled and if modular the mce-inject module loaded. This option is available in Linux 2.6.31 or later. NOTES
The mce-test package has a lot of input file examples. SEE ALSO
Intel 64 and IA32 Architectures Software Developer's manual, Volume 3, System programming guide Parts 1 and 2. Machine checks are described in Chapter 14 in Part1 and in Append ix E in Part2. Datasheet of your CPU. Intel OTC May 2009 MCE-INJECT(8)
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