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Special Forums UNIX and Linux Applications High Performance Computing Memory Barriers for (Ubuntu) Linux (i686) Post 302430141 by gorga on Wednesday 16th of June 2010 06:01:30 PM
Old 06-16-2010
Hi Corona, (small world Smilie)

Quote:
Originally Posted by Corona688
You could try using Linux futexes, which handle the nonblocking case completely in userspace, but I'm not sure what that'd do for memory barriers
I hadn't heard of futexes until you mentioned them, but I did some reading and it seems they still use atomic instructions to update shared variables. In that case I could just use one of GCC's built-in atomic operations like "__sync_fetch_ and_ add" or "__sync_bool_compare_and_swap" as described here...

Atomic Builtins - Using the GNU Compiler Collection (GCC)

The thing with these is they use the asm op-code "lock", which issues a hardware lock on the data-bus effectively locking every other process out of memory. Because I'm writing an application that should be scalable for a system with many cores, I'm discouraged by this.

Quote:
Besides, what if you need to move it to MIPS or something?
Could be a possibility, I believe they have made advances into highly parrallel architectures recently, but the project is at a research stage right now so if I can get it to work well on x86 that's good enough for now. I like the sound of this idea though...

Quote:
Could you perhaps reorder it to put prefix, instance, and state in order in memory? You could assemble the data in an MMX or SSE register, then overwrite several structure members in one assembly op.
This could be a good solution, but I'm not sure how to do it. Do you have any examples of similar code as a guide?

Quote:
One thought does occur to me. How large are these structures?
prefix and instance are both uint32_t while state is an enum (guess that means its a uint32_t also?).
 

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membar_ops(3C)															    membar_ops(3C)

NAME
membar_ops, membar_enter, membar_exit, membar_producer, membar_consumer - memory access synchronization barrier operations SYNOPSIS
#include <atomic.h> void membar_enter(void); void membar_exit(void); void membar_producer(void); void membar_consumer(void); The membar_enter() function is a generic memory barrier used during lock entry. It is placed after the memory operation that acquires the lock to guarantee that the lock protects its data. No stores from after the memory barrier will reach visibility and no loads from after the barrier will be resolved before the lock acquisition reaches global visibility. The membar_exit() function is a generic memory barrier used during lock exit. It is placed before the memory operation that releases the lock to guarantee that the lock protects its data. All loads and stores issued before the barrier will be resolved before the sub- sequent lock update reaches visibility. The membar_enter() and membar_exit() functions are used together to allow regions of code to be in relaxed store order and then ensure that the load or store order is maintained at a higher level. They are useful in the implementation of mutex exclusion locks. The membar_producer() function arranges for all stores issued before this point in the code to reach global visibility before any stores that follow. This is useful in producer modules that update a data item, then set a flag that it is available. The memory barrier guaran- tees that the available flag is not visible earlier than the updated data, thereby imposing store ordering. The membar_consumer() function arranges for all loads issued before this point in the code to be completed before any subsequent loads. This is useful in consumer modules that check if data is available and read the data. The memory barrier guarantees that the data is not sampled until after the available flag has been seen, thereby imposing load ordering. No values are returned. No errors are defined. See attributes(5) for descriptions of the following attributes: +-----------------------------+-----------------------------+ | ATTRIBUTE TYPE | ATTRIBUTE VALUE | +-----------------------------+-----------------------------+ |Interface Stability |Stable | +-----------------------------+-----------------------------+ |MT-Level |MT-Safe | +-----------------------------+-----------------------------+ atomic_add(3C), atomic_and(3C), atomic_bits(3C), atomic_cas(3C), atomic_dec(3C), atomic_inc(3C), atomic_ops(3C), atomic_or(3C), atomic_swap(3C), attributes(5), atomic_ops(9F) Atomic instructions (see atomic_ops(3C)) ensure global visibility of atomically-modified variables on completion. In a relaxed store order system, this does not guarantee that the visibility of other variables will be synchronized with the completion of the atomic instruction. If such synchronization is required, memory barrier instructions must be used. 14 Feb 2005 membar_ops(3C)
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