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Full Discussion: Pin Memory Statistics
Operating Systems AIX Pin Memory Statistics Post 302352007 by GarciasMuffin on Thursday 10th of September 2009 08:02:06 AM
Old 09-10-2009
Pin Memory Statistics

Hi,


We have an issue on our lpar where the pin memory usage slowly and regularly increases approx 1.5% a day until it reaches its 80% threshold
We have to regularly reboot the lpars to release the pin memory as we have found that killing all processes does not release it.

However, obviously this is not a real solution.

I have monitored any constantly running processes that increase in memory usage with time by monitoring the output of ps vg. The only one I found of any significance was xmwlm stats recording service which I stopped, but pin memory usage still increased at the same pace.

Is monitoring svmon -P going to help me find the cause of this issue and if so, monitoring which figure in following example of a process when running svmon -P, will show me the process is increasing in pinned memory usage to cause the increase we are seeing. I know the obvious answer would be 'the one that says pin above it' but there are three of them in the example.

Pid Command Inuse Pin Pgsp Virtual 64-bit Mthrd 16MB
53274 wait 12251 8399 0 12251 Y N N


PageSize Inuse Pin Pgsp Virtual
s 4 KB 12155 8319 0 12155
m 64 KB 6 5 0 6


Vsid Esid Type Description PSize Inuse Pin Pgsp Virtual
0 0 work kernel segment s 12155 8319 0 12155
2802e f00000002 work process private m 5 4 0 5



Many thanks for any answers.

Last edited by GarciasMuffin; 09-10-2009 at 10:12 AM.. Reason: Additional Info
 

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Netlist::Pin(3pm)					User Contributed Perl Documentation					 Netlist::Pin(3pm)

NAME
Verilog::Netlist::Pin - Pin on a Verilog Cell SYNOPSIS
use Verilog::Netlist; ... my $pin = $cell->find_pin ('pinname'); print $pin->name; DESCRIPTION
A Verilog::Netlist::Pin object is created by Verilog::Netlist::Cell for for each pin connection on a cell. A Pin connects a net in the current design to a port on the instantiated cell's module. ACCESSORS
See also Verilog::Netlist::Subclass for additional accessors and methods. $self->cell Reference to the Verilog::Netlist::Cell the pin is under. $self->comment Returns any comments following the definition. keep_comments=>1 must be passed to Verilog::Netlist::new for comments to be retained. $self->delete Delete the pin from the cell it's under. $self->module Reference to the Verilog::Netlist::Module the pin is in. $self->name The name of the pin. May have extra characters to make vectors connect, generally portname is a more readable version. There may be multiple pins with the same portname, only one pin has a given name. $self->net Reference to the Verilog::Netlist::Net the pin connects to. Only valid after a link. $self->netlist Reference to the Verilog::Netlist the pin is in. $self->netname The net name the pin connects to. $self->portname The name of the port connected to. $self->port Reference to the Verilog::Netlist::Port the pin connects to. Only valid after a link. MEMBER FUNCTIONS
See also Verilog::Netlist::Subclass for additional accessors and methods. $self->lint Checks the pin for errors. Normally called by Verilog::Netlist::lint. $self->dump Prints debugging information for this pin. DISTRIBUTION
Verilog-Perl is part of the <http://www.veripool.org/> free Verilog EDA software tool suite. The latest version is available from CPAN and from http://www.veripool.org/verilog-perl <http://www.veripool.org/verilog-perl>. Copyright 2000-2012 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. AUTHORS
Wilson Snyder <wsnyder@wsnyder.org> SEE ALSO
Verilog-Perl, Verilog::Netlist::Subclass Verilog::Netlist perl v5.14.2 2012-05-04 Netlist::Pin(3pm)
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