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Top Forums Shell Programming and Scripting perl help to split big verilog file into smaller ones for each module Post 302315588 by return_user on Tuesday 12th of May 2009 08:19:21 PM
Old 05-12-2009
Quote:
Originally Posted by vgersh99
You probably have line(s) before the first "module" line.
Code:
awk '$1 == "module" { file= $2 ".v" } file != ""{print > file} $1 == "endmodule" {close(file); file=""}' intxt.txt

Thanks this one works better but what if my module line is like
module 1a_ext(a, b);
I just want the output filename to be
1a_ext.v
but its putting
1a_ext(a,.v
So how do we specify the output filename as the string between module and '(' ?
Thank you .
 

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EditFiles(3pm)						User Contributed Perl Documentation					    EditFiles(3pm)

NAME
Verilog::EditFiles - Split Verilog modules into separate files. SYNOPSIS
See splitmodule command. use Verilog::EditFiles; my $split = Verilog::EditFiles->new (outdir => "processed_rtl", translate_synthesis => 0, lint_header => undef, celldefine => 1, ); $split->read_and_split(glob("inbound_rtl/*.v")); $split->write_files(); $split->edit_file(filename=>"foo", cb => sub { return $_[0]; }); DESCRIPTION
Verilog::EditFiles provides a easy way to split library Verilog files that contain multiple modules into many files with one module per file. FUNCTIONS
new (...) Create a new Verilog::EditFiles object. Named parameters may be specified: celldefine If true, add "`celldefine" before every module statement. lint_command For the write_lint method, the name of the linter to use. Defaults to "vlint --brief". lint_header If defined, add the provided text before every module statement. Generally used to insert lint off pragmas. outdir Name of the directory to write the output modules to. Defaults to ".". program Name of the program to add to comments. Defaults to "Verilog::EditFiles". timescale_header If defined, add the provided text before every module statement. Generally set to the next needed to #include a timescale file. Use with timescale_removal. timescale_removal If set, remove any `timescales. translate_synthesis If 1, replace any synopsys translate on/offs with "`ifdef SYNTHESIS" and "`endif"s. If set to a string, use that string instead of "SYNTHESIS". v_suffix The suffix to add to convert a module name into a filename. Defaults to ".v". verbose If true, print what files are being read and written. $self->read_and_split ([filenames]) Read from the specified filenames. If there is no module statement in the file, assume it is a include file, and when write_files is called, place all of the file contents into the output. If there is a module statement, when write_files is called place all following output into a file named based on the module, with .v added. $self->write_files() Write all of the files created by read_and_split to the outdir. $self->write_lint([filename=>...]) Create a shell script that will lint every file created by write_files. If a "filename" parameter is not provided, "0LINT.sh" will be written in the default outdir. $self->edit_file(filename=>..., cb=>sub{...}) Read a file, edit it with the provided callback, and save it if it has changed. The "filename" parameter is the filename to read. The "write_filename" parameter is the filename to write, defaulting to the same name as the filename to read. The "cb" parameter is a reference to a callback which takes the string of file contents and returns the string to write back. Often the callback will simply perform a search and replace. DISTRIBUTION
Verilog-Perl is part of the <http://www.veripool.org/> free Verilog EDA software tool suite. The latest version is available from CPAN and from http://www.veripool.org/verilog-perl <http://www.veripool.org/verilog-perl>. Copyright 2006-2012 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. AUTHORS
Wilson Snyder <wsnyder@wsnyder.org> SEE ALSO
Verilog-Perl perl v5.14.2 2012-05-04 EditFiles(3pm)
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