12-31-2008
lom to ok prompt in netra 1280
HI group,
Can anyone please suggest what can be the problem when we send poweron command on lom it again comes to lom and show following error
what does it means
lom>poweron
/N0/PS0: already on
/N0/PS1: already on
/N0/PS2: already on
/N0/PS3: already on
Powering boards on ...
Tue Dec 30 23:33:06 noname.example.com lom: Excluded unusable, unlicensed, faile
d or disabled board: /N0/IB6
Testing CPU Boards ...
Loading the test table from board SB0 PROM 0 ...
{/N0/SB0/P0} Running CPU POR and Set Clocks
{/N0/SB0/P1} Running CPU POR and Set Clocks
{/N0/SB0/P0} @(#) lpost 5.18.1 2004/12/09 12:32
{/N0/SB0/P1} @(#) lpost 5.18.1 2004/12/09 12:32
{/N0/SB0/P0} Copyright 2001-2004 Sun Microsystems, Inc. All rights reserved.
{/N0/SB0/P2} Running CPU POR and Set Clocks
{/N0/SB0/P1} Copyright 2001-2004 Sun Microsystems, Inc. All rights reserved.
{/N0/SB0/P3} Running CPU POR and Set Clocks
{/N0/SB0/P2} @(#) lpost 5.18.1 2004/12/09 12:32
{/N0/SB0/P0} Use is subject to license terms.
{/N0/SB0/P1} Use is subject to license terms.
{/N0/SB0/P3} @(#) lpost 5.18.1 2004/12/09 12:32
{/N0/SB0/P2} Copyright 2001-2004 Sun Microsystems, Inc. All rights reserved.
{/N0/SB0/P3} Copyright 2001-2004 Sun Microsystems, Inc. All rights reserved.
{/N0/SB0/P2} Use is subject to license terms.
{/N0/SB0/P3} Use is subject to license terms.
{/N0/SB0/P2} Running Basic CPU
{/N0/SB0/P3} Running Basic CPU
{/N0/SB0/P2} @(#) lpost 5.18.1 2004/12/09 12:32
{/N0/SB0/P3} @(#) lpost 5.18.1 2004/12/09 12:32
{/N0/SB0/P2} Copyright 2001-2004 Sun Microsystems, Inc. All rights reserved.
{/N0/SB0/P3} Copyright 2001-2004 Sun Microsystems, Inc. All rights reserved.
{/N0/SB0/P2} Use is subject to license terms.
{/N0/SB0/P0} Running Basic CPU
{/N0/SB0/P3} Use is subject to license terms.
{/N0/SB0/P1} Running Basic CPU
{/N0/SB0/P0} @(#) lpost 5.18.1 2004/12/09 12:32
{/N0/SB0/P1} @(#) lpost 5.18.1 2004/12/09 12:32
{/N0/SB0/P0} Copyright 2001-2004 Sun Microsystems, Inc. All rights reserved.
{/N0/SB0/P1} Copyright 2001-2004 Sun Microsystems, Inc. All rights reserved.
{/N0/SB0/P0} Use is subject to license terms.
{/N0/SB0/P2} Subtest: Setting Fireplane Config Registers
{/N0/SB0/P1} Use is subject to license terms.
{/N0/SB0/P3} Subtest: Setting Fireplane Config Registers
{/N0/SB0/P0} Subtest: Setting Fireplane Config Registers
{/N0/SB0/P1} Subtest: Setting Fireplane Config Registers
{/N0/SB0/P2} Subtest: Display CPU Version, frequency
{/N0/SB0/P3} Subtest: Display CPU Version, frequency
{/N0/SB0/P0} Subtest: Display CPU Version, frequency
{/N0/SB0/P1} Subtest: Display CPU Version, frequency
{/N0/SB0/P2} Version register = 003e0015.b0000507
{/N0/SB0/P3} Version register = 003e0015.b0000507
{/N0/SB0/P0} Version register = 003e0015.b0000507
{/N0/SB0/P1} Version register = 003e0015.b0000507
{/N0/SB0/P2} Ecache Control Register 00000000.07c55400
{/N0/SB0/P3} Ecache Control Register 00000000.07c55400
{/N0/SB0/P0} Ecache Control Register 00000000.07c55400
{/N0/SB0/P1} Ecache Control Register 00000000.07c55400
{/N0/SB0/P2} Cpu/System ratio = 8, cpu actual frequency = 1200
{/N0/SB0/P3} Cpu/System ratio = 8, cpu actual frequency = 1200
{/N0/SB0/P0} Cpu/System ratio = 8, cpu actual frequency = 1200
{/N0/SB0/P1} Cpu/System ratio = 8, cpu actual frequency = 1200
{/N0/SB0/P2} @(#) lpost 5.18.1 2004/12/09 12:32
{/N0/SB0/P3} @(#) lpost 5.18.1 2004/12/09 12:32
{/N0/SB0/P0} @(#) lpost 5.18.1 2004/12/09 12:32
{/N0/SB0/P1} @(#) lpost 5.18.1 2004/12/09 12:32
{/N0/SB0/P2} Copyright 2001-2004 Sun Microsystems, Inc. All rights reserved.
{/N0/SB0/P3} Copyright 2001-2004 Sun Microsystems, Inc. All rights reserved.
{/N0/SB0/P0} Copyright 2001-2004 Sun Microsystems, Inc. All rights reserved.
{/N0/SB0/P1} Copyright 2001-2004 Sun Microsystems, Inc. All rights reserved.
{/N0/SB0/P2} Use is subject to license terms.
{/N0/SB0/P3} Use is subject to license terms.
{/N0/SB0/P0} Use is subject to license terms.
{/N0/SB0/P1} Use is subject to license terms.
{/N0/SB0/P2} Subtest: I-Cache Initialization
{/N0/SB0/P3} Subtest: I-Cache Initialization
{/N0/SB0/P0} Subtest: I-Cache Initialization
{/N0/SB0/P1} Subtest: I-Cache Initialization
{/N0/SB0/P2} Subtest: D-Cache Initialization
{/N0/SB0/P3} Subtest: D-Cache Initialization
{/N0/SB0/P0} Subtest: D-Cache Initialization
{/N0/SB0/P1} Subtest: D-Cache Initialization
{/N0/SB0/P2} Subtest: W-Cache Initialization
{/N0/SB0/P3} Subtest: W-Cache Initialization
{/N0/SB0/P0} Subtest: W-Cache Initialization
{/N0/SB0/P1} Subtest: W-Cache Initialization
{/N0/SB0/P2} Subtest: P-Cache Initialization
{/N0/SB0/P3} Subtest: P-Cache Initialization
{/N0/SB0/P0} Subtest: P-Cache Initialization
{/N0/SB0/P1} Subtest: P-Cache Initialization
{/N0/SB0/P2} Subtest: Branch Prediction Initialization
{/N0/SB0/P3} Subtest: Branch Prediction Initialization
{/N0/SB0/P0} Subtest: Branch Prediction Initialization
{/N0/SB0/P1} Subtest: Branch Prediction Initialization
{/N0/SB0/P2} Subtest: E-Cache Global Variables Initialization
{/N0/SB0/P3} Subtest: E-Cache Global Variables Initialization
{/N0/SB0/P0} Subtest: E-Cache Global Variables Initialization
{/N0/SB0/P1} Subtest: E-Cache Global Variables Initialization
{/N0/SB0/P2} Subtest: Fast Init. Verification Test
{/N0/SB0/P3} Subtest: Fast Init. Verification Test
{/N0/SB0/P0} Subtest: Fast Init. Verification Test
{/N0/SB0/P1} Subtest: Fast Init. Verification Test
{/N0/SB0/P0} Running Enable MMU
{/N0/SB0/P1} Running Enable MMU
{/N0/SB0/P1} Subtest: IMMU Initialization
{/N0/SB0/P0} Subtest: IMMU Initialization
{/N0/SB0/P2} Running Enable MMU
{/N0/SB0/P3} Running Enable MMU
{/N0/SB0/P0} Subtest: DMMU Initialization
{/N0/SB0/P2} Subtest: IMMU Initialization
{/N0/SB0/P1} Subtest: DMMU Initialization
{/N0/SB0/P3} Subtest: IMMU Initialization
{/N0/SB0/P2} Subtest: DMMU Initialization
{/N0/SB0/P3} Subtest: DMMU Initialization
{/N0/SB0/P2} Subtest: Map LPOST to local space
{/N0/SB0/P3} Subtest: Map LPOST to local space
{/N0/SB0/P2} Running FPU Tests
{/N0/SB0/P3} Running FPU Tests
{/N0/SB0/P0} Running FPU Tests
{/N0/SB0/P1} Running FPU Tests
{/N0/SB0/P0} Subtest: Map LPOST to local space
{/N0/SB0/P1} Subtest: Map LPOST to local space
{/N0/SB0/P0} Running Basic Ecache
{/N0/SB0/P1} Running Basic Ecache
{/N0/SB0/P0} Subtest: E-Cache Initialization of first 1K
{/N0/SB0/P2} Running Basic Ecache
{/N0/SB0/P1} Subtest: E-Cache Initialization of first 1K
{/N0/SB0/P3} Running Basic Ecache
{/N0/SB0/P2} Subtest: E-Cache Initialization of first 1K
{/N0/SB0/P3} Subtest: E-Cache Initialization of first 1K
{/N0/SB0/P2} Subtest: E-Cache Initialization
{/N0/SB0/P0} Subtest: E-Cache Initialization
{/N0/SB0/P1} Subtest: E-Cache Initialization
{/N0/SB0/P3} Subtest: E-Cache Initialization
{/N0/SB0/P2} Running Memory Registers Tests
{/N0/SB0/P3} Running Memory Registers Tests
{/N0/SB0/P2} Subtest: Disable Memory Controllers
{/N0/SB0/P3} Subtest: Disable Memory Controllers
{/N0/SB0/P0} Running Memory Registers Tests
{/N0/SB0/P1} Running Memory Registers Tests
{/N0/SB0/P0} Subtest: Disable Memory Controllers
{/N0/SB0/P1} Subtest: Disable Memory Controllers
{/N0/SB0/P0} Running Memory Configuration Tests
{/N0/SB0/P1} Running Memory Configuration Tests
{/N0/SB0/P0} Subtest: Memory Controller Configuration
{/N0/SB0/P1} Subtest: Memory Controller Configuration
{/N0/SB0/P2} Running Memory Configuration Tests
{/N0/SB0/P3} Running Memory Configuration Tests
{/N0/SB0/P2} Subtest: Memory Controller Configuration
{/N0/SB0/P3} Subtest: Memory Controller Configuration
{/N0/SB0/P1} Subtest: UP Memory Clear
{/N0/SB0/P0} Subtest: UP Memory Clear
{/N0/SB0/P2} Subtest: UP Memory Clear
{/N0/SB0/P3} Subtest: UP Memory Clear
{/N0/SB0/P0} Running Memory Tests
{/N0/SB0/P1} Running Memory Tests
{/N0/SB0/P2} Running Memory Tests
{/N0/SB0/P3} Running Memory Tests
{/N0/SB0/P0} Running Advanced CPU Tests
{/N0/SB0/P1} Running Advanced CPU Tests
{/N0/SB0/P2} Running Advanced CPU Tests
{/N0/SB0/P3} Running Advanced CPU Tests
{/N0/SB0/P0} Running CPU ECC Tests
{/N0/SB0/P1} Running CPU ECC Tests
{/N0/SB0/P2} Running CPU ECC Tests
{/N0/SB0/P3} Running CPU ECC Tests
{/N0/SB0/P2} Running System Level Tests
{/N0/SB0/P3} Running System Level Tests
{/N0/SB0/P0} Running System Level Tests
{/N0/SB0/P1} Running System Level Tests
{/N0/SB0/P0} Running Board Memory Interleave
{/N0/SB0/P1} Running Board Memory Interleave
{/N0/SB0/P0} Subtest: Board Memory Interleave Configuration
{/N0/SB0/P1} Subtest: Board Memory Interleave Configuration
{/N0/SB0/P2} Running Board Memory Interleave
{/N0/SB0/P3} Running Board Memory Interleave
{/N0/SB0/P2} Subtest: Board Memory Interleave Configuration
{/N0/SB0/P3} Subtest: Board Memory Interleave Configuration
{/N0/SB0/P0} Passed
{/N0/SB0/P1} Passed
{/N0/SB0/P2} Passed
{/N0/SB0/P3} Passed
Testing IO Boards ...
Tue Dec 30 23:33:56 noname.example.com lom: No usable Io board in domain.
lom>
Regards
Sameer
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